Merge pull request #4 from michaelhelper/main

Added Verilog function code and tests for each function

.history/verilog files/CUP_20231130142427.sv

@@ -0,0 +1,81 @@
+module CPU (
+    input wire clk,
+    input wire reset,
+    inout wire [15:0] AC,  // Accumulator
+    inout wire [15:0] M[0:16383]  // Main memory
+);
+
+    // Declare the necessary registers
+    reg [15:0] PC;  // Program Counter
+    reg [15:0] IR;  // Instruction Register
+    reg [15:0] MAR;  // Memory Address Register
+    reg [15:0] MBR;  // Memory Buffer Register
+
+    // Fetch instruction
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            PC <= 16'b0;
+        end else begin
+            MAR <= PC;
+            IR <= M[MAR];
+            PC <= PC + 1;
+        end
+    end
+
+    // Decode and execute instruction
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            AC <= 16'b0;
+        end else begin
+            case (IR[15:12])  // Assume the opcode is in the upper 4 bits of the instruction
+                4'b0000: begin  // LOAD X
+                    MAR <= IR[11:0];  // Assume the operand is in the lower 12 bits of the instruction
+                    MBR <= M[MAR];
+                    AC <= MBR;
+                end
+                4'b0001: begin  // STORE X
+                    MAR <= IR[11:0];
+                    M[MAR] <= AC;
+                end
+                4'b0010: begin  // ADD X
+                    MAR <= IR[11:0];
+                    MBR <= M[MAR];
+                    AC <= AC + MBR;
+                end
+                4'b0011: begin  // SUB X
+                    MAR <= IR[11:0];
+                    MBR <= M[MAR];
+                    AC <= AC - MBR;
+                end
+                4'b0100: begin  // AND X
+                    MAR <= IR[11:0];
+                    MBR <= M[MAR];
+                    AC <= AC & MBR;
+                end
+                4'b0101: begin  // OR X
+                    MAR <= IR[11:0];
+                    MBR <= M[MAR];
+                    AC <= AC | MBR;
+                end
+                4'b0110: begin  // NOT
+                    AC <= ~AC;
+                end
+                4'b0111: begin  // JUMP X
+                    PC <= IR[11:0];
+                end
+                4'b1000: begin  // JZ X
+                    if (AC == 16'b0) begin
+                        PC <= IR[11:0];
+                    end
+                end
+                4'b1001: begin  // HALT
+                    PC <= PC - 1;
+                end
+                default: begin  // NOP
+                    // Do nothing
+                end
+            endcase
+        end
+    end
+
+endmodule

.history/verilog files/CUP_testbench_20231130142403.sv

@@ -0,0 +1,15 @@
+initial begin
+    // Initialize signals
+    clk = 0;
+    reset = 1;
+    AC = 16'b0;
+    // Initialize main memory with the binary representation of the assembly program
+    M[0] = 16'b0000_0000_0010;  // LOAD 0x2
+    M[1] = 16'b0010_0000_0011;  // ADD 0x3
+    M[2] = 16'b0001_0000_0100;  // STORE 0x4
+    M[3] = 16'b1001_0000_0000;  // HALT
+    // Initialize the rest of main memory to zero
+    for (integer i = 4; i < 16384; i = i + 1) begin
+        M[i] = 16'b0;
+    end
+end

.history/verilog files/CUP_testbench_20231130142411.sv

@@ -0,0 +1,17 @@
+
+
+initial begin
+    // Initialize signals
+    clk = 0;
+    reset = 1;
+    AC = 16'b0;
+    // Initialize main memory with the binary representation of the assembly program
+    M[0] = 16'b0000_0000_0010;  // LOAD 0x2
+    M[1] = 16'b0010_0000_0011;  // ADD 0x3
+    M[2] = 16'b0001_0000_0100;  // STORE 0x4
+    M[3] = 16'b1001_0000_0000;  // HALT
+    // Initialize the rest of main memory to zero
+    for (integer i = 4; i < 16384; i = i + 1) begin
+        M[i] = 16'b0;
+    end
+end

.history/verilog files/CUP_testbench_20231130142412.sv

@@ -0,0 +1,20 @@
+LOAD 0x2
+ADD 0x3
+STORE 0x4
+HALT
+
+initial begin
+    // Initialize signals
+    clk = 0;
+    reset = 1;
+    AC = 16'b0;
+    // Initialize main memory with the binary representation of the assembly program
+    M[0] = 16'b0000_0000_0010;  // LOAD 0x2
+    M[1] = 16'b0010_0000_0011;  // ADD 0x3
+    M[2] = 16'b0001_0000_0100;  // STORE 0x4
+    M[3] = 16'b1001_0000_0000;  // HALT
+    // Initialize the rest of main memory to zero
+    for (integer i = 4; i < 16384; i = i + 1) begin
+        M[i] = 16'b0;
+    end
+end

.history/verilog files/CUP_testbench_20231130142416.sv

@@ -0,0 +1,20 @@
+// LOAD 0x2
+// ADD 0x3
+// STORE 0x4
+// HALT
+
+initial begin
+    // Initialize signals
+    clk = 0;
+    reset = 1;
+    AC = 16'b0;
+    // Initialize main memory with the binary representation of the assembly program
+    M[0] = 16'b0000_0000_0010;  // LOAD 0x2
+    M[1] = 16'b0010_0000_0011;  // ADD 0x3
+    M[2] = 16'b0001_0000_0100;  // STORE 0x4
+    M[3] = 16'b1001_0000_0000;  // HALT
+    // Initialize the rest of main memory to zero
+    for (integer i = 4; i < 16384; i = i + 1) begin
+        M[i] = 16'b0;
+    end
+end

.history/verilog files/design_20231129171127.sv

@@ -0,0 +1,144 @@
+`timescale 1ns / 1ps
+
+// Accumulator
+module Accumulator (
+    input wire clk,
+    input wire reset,
+    input wire [15:0] data_in,
+    output reg [15:0] acc
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        acc <= 16'b0;
+    end else begin
+        acc <= acc + data_in;
+    end
+end
+
+endmodule
+
+// Program Counter
+module ProgramCounter (
+    input wire clk,
+    input wire reset,
+    input wire jump,
+    input wire [15:0] jump_addr,
+    output reg [15:0] pc
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        pc <= 16'b0;
+    end else if (jump) begin
+        pc <= jump_addr;
+    end else begin
+        if (pc == 16'hFFFF) begin
+            $display("Warning: Program Counter overflow");
+            pc <= 16'b0;
+        end else begin
+            pc <= pc + 1;
+        end
+    end
+end
+
+endmodule
+
+// Memory Access Register
+ module MAR (
+    input wire clk,
+    input wire reset,
+    input wire [15:0] addr_in,
+    output reg [15:0] addr_out
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        addr_out <= 16'b0;
+    end else begin
+        addr_out <= addr_in;
+    end
+end
+
+endmodule
+
+// Memory Buffer Register
+module MBR (
+    input wire clk,
+    input wire reset,
+    input wire [15:0] data_in,
+    output reg [15:0] data_out
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        data_out <= 16'b0;
+    end else begin
+        data_out <= data_in;
+    end
+end
+
+endmodule
+
+// Instruction Register
+module IR (
+    input wire clk,
+    input wire reset,
+    input wire [15:0] instr_in,
+    output reg [15:0] instr_out
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        instr_out <= 16'b0;
+    end else begin
+        instr_out <= instr_in;
+    end
+end
+
+endmodule
+
+// Arithmetic and Logic Unit
+module ALU (
+    input wire [2:0] opcode,
+    input wire [15:0] operand1,
+    input wire [15:0] operand2,
+    output reg [15:0] result
+);
+
+always @(*) begin
+    case (opcode)
+        3'b000: result = operand1 + operand2;  // Addition
+        3'b001: result = operand1 - operand2;  // Subtraction
+        3'b010: result = operand1 & operand2;  // Bitwise AND
+        3'b011: result = operand1 | operand2;  // Bitwise OR
+        3'b100: result = operand1 ^ operand2;  // Bitwise XOR
+        default: result = 16'b0;               // Default case
+    endcase
+end
+
+endmodule
+
+// Main memory
+module MainMemory (
+    input wire clk,
+    input wire [15:0] addr,
+    input wire [15:0] data_in,
+    input wire write_enable,
+    output reg [15:0] data_out
+);
+
+    // Declare a 16Ki x 16 memory array
+    reg [15:0] memory [0:16383];
+
+    always @(posedge clk) begin
+        if (write_enable) begin
+            // Write data_in to the memory location specified by addr
+            memory[addr] <= data_in;
+        end else begin
+            // Read data from the memory location specified by addr
+            data_out <= memory[addr];
+        end
+    end
+
+endmodule