add wr_type

HITSZ-NSCSCC22 · Jun 25, 2022 · 20b9be9 · 20b9be9
1 parent ac8c1a3
commit 20b9be9
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Showing 5 changed files with 17 additions and 5 deletions.
diff --git a/src/vsrc/AXI/README.md b/src/vsrc/AXI/README.md
@@ -223,7 +223,7 @@
 | rd_type(wr_type) | arzie(awsize) |字节数|
 |:----:|:----:|:----:|
 |3'b000|3'b000|1|
-|3'b001|3'b00|2|
+|3'b001|3'b001|2|
 |3'b010|3'b010|4|
 |3'b011|3'b011|8|
 |3'b100|3'b100|16|
diff --git a/src/vsrc/core_types.sv b/src/vsrc/core_types.sv
@@ -181,6 +181,7 @@ package core_types;
         logic [`RegBus] data;
         logic uncache_en;
         logic [2:0] rd_type;
+        logic [2:0]wr_type;
     } mem_cache_struct;
 
     typedef struct packed {

diff --git a/src/vsrc/cpu_top.sv b/src/vsrc/cpu_top.sv
@@ -116,6 +116,7 @@ module cpu_top
     logic [15:0] dcache_axi_wstrb; // Byte selection
     logic [127:0] axi_dcache_data; // AXI Read result
     logic [2:0] dcache_rd_type;
+    logic [2:0] dcache_wr_type;
 
     logic [`RegBus] cache_mem_data;
     logic mem_data_ok,mem_addr_ok;
@@ -145,7 +146,7 @@ module cpu_top
         .dcache_ret_valid_o(axi_dcache_rvalid),
         .dcache_ret_last_o(), // same as ICache
         .dcache_wr_req_i(dcache_axi_wreq),
-        .dcache_wr_type_i(3'b100), 
+        .dcache_wr_type_i(dcache_wr_type), 
         .dcache_wr_data(dcache_axi_data),
         .dcache_wr_rdy(axi_dcache_wr_rdy),
         .write_ok(), // Used in conherent instructions, unused for now
@@ -196,11 +197,13 @@ module cpu_top
     logic [3:0] mem_cache_sel;
     logic [31:0] mem_cache_addr,mem_cache_data;
     logic [1:0] wb_dcache_flush; // flush dcache if excp
+    logic [2:0]mem_cache_wr_type;
 
     assign mem_cache_ce = mem_cache_signal[0].ce | mem_cache_signal[1].ce;
     assign mem_cache_we = mem_cache_signal[0].we | mem_cache_signal[1].we;
     assign mem_cache_sel = mem_cache_signal[0].we ? mem_cache_signal[0].sel : mem_cache_signal[1].we ? mem_cache_signal[1].sel : 0;
     assign mem_cache_rd_type = mem_cache_signal[0].ce ? mem_cache_signal[0].rd_type : mem_cache_signal[1].ce ? mem_cache_signal[1].rd_type : 0;
+    assign mem_cache_wr_type = mem_cache_signal[0].ce ? mem_cache_signal[0].wr_type : mem_cache_signal[1].ce ? mem_cache_signal[1].wr_type : 0;
     assign mem_cache_addr = mem_cache_signal[0].addr | mem_cache_signal[1].addr;
     assign mem_cache_data = mem_cache_signal[0].we ? mem_cache_signal[0].data : mem_cache_signal[1].we ? mem_cache_signal[1].data : 0;
 
@@ -217,6 +220,7 @@ module cpu_top
         .wstrb     (mem_cache_sel),
         .wdata     (mem_cache_data),
         .rd_type_i (mem_cache_rd_type),
+        .wr_type_i (mem_cache_wr_type),
         .flush_i    (wb_dcache_flush!=2'b0), // If excp occurs, flush DCache
         .addr_ok   (mem_addr_ok),
         .data_ok   (mem_data_ok),
@@ -231,7 +235,7 @@ module cpu_top
         .ret_last  (),
         .ret_data  (axi_dcache_data),
         .wr_req    (dcache_axi_wreq),
-        .wr_type   (),
+        .wr_type   (dcache_wr_type),
         .wr_addr   (dcache_axi_waddr),
         .wr_wstrb  (dcache_axi_wstrb),
         .wr_data   (dcache_axi_data),

diff --git a/src/vsrc/dummy_dcache.sv b/src/vsrc/dummy_dcache.sv
@@ -12,6 +12,7 @@ module dummy_dcache (
     input logic [3:0] wstrb,  //写字节使能信号
     input logic [31:0] wdata,  //写数据
     input logic [2:0] rd_type_i, //读请求类型：3'b000: 字节；3'b001: 半字；3'b010: 字；3'b100：Cache行
+    input logic [2:0] wr_type_i,
     input logic flush_i, // 冲刷信号，如果出于某种原因需要取消写事务，CPU拉高此信号
     output logic addr_ok,             //该次请求的地址传输OK，读：地址被接收；写：地址和数据被接收
     output logic data_ok,             //该次请求的数据传输Ok，读：数据返回；写：数据写入完成
@@ -97,8 +98,8 @@ module dummy_dcache (
     end
 
 
-    assign rd_type = rd_type_i;
-    assign wr_type = 3'b010;  // word
+    assign rd_type = (uncache==0)?rd_type_i:3'b100;
+    assign wr_type = (uncache==0)?wr_type_i:3'b100;  // word
     always_comb begin
         // Default signal
         rd_addr  = 0;

diff --git a/src/vsrc/pipeline/4_mem/mem.sv b/src/vsrc/pipeline/4_mem/mem.sv
@@ -141,6 +141,7 @@ module mem
         signal_cache_o = 0;
         signal_o.store_data = 0;
         signal_cache_o.rd_type = 0;
+        signal_cache_o.wr_type=0;
         signal_o.cacop_en = cacop_en;
         signal_o.icache_op_en = icache_op_en;
         signal_o.cacop_op = cacop_op;
@@ -253,6 +254,7 @@ module mem
                 signal_o.wreg = `WriteEnable;
                 signal_cache_o.we = `WriteEnable;
                 signal_cache_o.ce = `ChipEnable;
+                signal_cache_o.wr_type=3'b000;
                 signal_cache_o.data = {reg2_i[7:0], reg2_i[7:0], reg2_i[7:0], reg2_i[7:0]};
                 case (mem_addr[1:0])
                     2'b11: begin
@@ -278,6 +280,7 @@ module mem
                 signal_o.wreg = `WriteEnable;
                 signal_cache_o.we = `WriteEnable;
                 signal_cache_o.ce = `ChipEnable;
+                signal_cache_o.wr_type=3'b001;
                 signal_cache_o.data = {reg2_i[15:0], reg2_i[15:0]};
                 case (mem_addr[1:0])
                     2'b10: begin
@@ -298,6 +301,7 @@ module mem
                 signal_o.wreg = `WriteEnable;
                 signal_cache_o.we = `WriteEnable;
                 signal_cache_o.ce = `ChipEnable;
+                signal_cache_o.wr_type=3'b010;
                 signal_cache_o.data = reg2_i;
                 signal_cache_o.sel = 4'b1111;
                 signal_o.store_data = reg2_i;
@@ -319,6 +323,7 @@ module mem
                     signal_cache_o.ce = `ChipEnable;
                     signal_cache_o.data = reg2_i;
                     signal_cache_o.sel = 4'b1111;
+                    signal_cache_o.wr_type=3'b010;
                     LLbit_we_o = 1'b1;
                     LLbit_value_o = 1'b0;
                     signal_o.wreg = `WriteEnable;
@@ -329,6 +334,7 @@ module mem
                     signal_o.wreg = `WriteEnable;
                     signal_o.store_data = 0;
                     signal_o.wdata = 32'b0;
+                    signal_cache_o.wr_type=3'b000;
                 end
             end
             default: begin