feat: connect tlb tag

src/vsrc/cpu_top.sv

@@ -307,6 +307,7 @@ module cpu_top (
         .inst_addr_trans_en(inst_addr_trans_en),
         .dmw0_en(tlb_inst_i.dmw0_en),
         .dmw1_en(tlb_inst_i.dmw1_en),
+        .inst_tlb_tag(tlb_inst_o.tag),
         .inst_tlb_found(tlb_inst_o.tlb_found),
         .inst_tlb_v(tlb_inst_o.tlb_v),
         .inst_tlb_d(tlb_inst_o.tlb_d),

src/vsrc/frontend/frontend.sv

@@ -46,6 +46,7 @@ module frontend #(
     output logic inst_addr_trans_en,
     output logic dmw0_en,
     output logic dmw1_en,
+    input logic [19:0] inst_tlb_tag,
     input logic inst_tlb_found,
     input logic inst_tlb_v,
     input logic inst_tlb_d,

src/vsrc/tlb.sv

@@ -37,12 +37,12 @@ module tlb (
     logic [5:0] s1_ps;
     logic [19:0] s1_ppn;
 
-    logic  we;
-    logic  [4:0] w_index;
+    logic we;
+    logic [4:0] w_index;
     tlb_wr_port w_port;
 
 
-    logic  [4:0] r_index;
+    logic [4:0] r_index;
     tlb_wr_port r_port;
 
     logic [31:0] inst_vaddr_buffer;
@@ -136,7 +136,7 @@ module tlb (
     );
 
     //debug用
-    logic dmw0_en,dmw1_en,cacop_test;
+    logic dmw0_en, dmw1_en, cacop_test;
     assign dmw0 = data_i.dmw0_en;
     assign dmw1 = data_i.dmw1_en;
     assign cacop_test = data_i.cacop_op_mode_di;