Merge branch 'dev'

HITSZ-NSCSCC22 · Mar 29, 2022 · e534b34 · e534b34
2 parents 7a7aeb5 + c52867d
commit e534b34
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Showing 5 changed files with 50 additions and 37 deletions.
diff --git a/src/SimTop.v b/src/SimTop.v
@@ -109,7 +109,6 @@ module SimTop(
   reg [7:0] index = 0;
   wire reset_n;
   assign reset_n = ~reset;
-  wire [63:0] ram_rdata;
 
 
 

diff --git a/src/vsrc/cpu_top.v b/src/vsrc/cpu_top.v
@@ -1,6 +1,6 @@
 `include "defines.v"
 `include "pc_reg.v"
-`include "pc2_reg.v"
+`include "if_buffer.v"
 `include "regfile.v"
 `include "pipeline/1_fetch/if_id.v"
 `include "pipeline/2_decode/id.v"
@@ -59,17 +59,19 @@ module cpu_top (
          );
 
   wire [`InstAddrBus]pc2;
-  pc2_reg u_pc2_reg(
-            .clk(clk),
-            .rst(rst),
-            .pc(pc),
-            .branch_flag_i(branch_flag),
-            .pc2(pc2)
-          );
+  if_buffer if_buffer_1(
+              .clk(clk),
+              .rst(rst),
+              .pc_i(pc),
+              .branch_flag_i(branch_flag),
+              .pc_valid(if_inst_valid),
+              .pc_o(pc2)
+            );
 
 
   wire[`InstAddrBus] id_pc;
   wire[`InstBus] id_inst;
+  wire if_inst_valid;
 
   //  wire if_id_instr_invalid;
   if_id u_if_id(
@@ -79,7 +81,7 @@ module cpu_top (
           .if_inst_i(ram_rdata_i),
           .id_pc_o(id_pc),
           .id_inst_o(id_inst),
-          //          .instr_invalid(if_id_instr_invalid) // <- ctrl block
+          .if_inst_valid(if_inst_valid),
           .branch_flag_i(branch_flag)
         );
 

diff --git a/src/vsrc/if_buffer.v b/src/vsrc/if_buffer.v
@@ -0,0 +1,32 @@
+//to keep PC and inst_o corresponding
+`include "defines.v"
+module if_buffer (
+    input wire clk,
+    input wire rst,
+    input wire [`InstAddrBus] pc_i,
+
+    input wire branch_flag_i,
+    output reg [`InstAddrBus] pc_o,
+    output reg pc_valid
+  );
+
+  always @(posedge clk)
+    begin
+      if(rst)
+        begin
+          pc_o <= `ZeroWord;
+          pc_valid <= `InstInvalid;
+        end
+      else if(branch_flag_i == `Branch)
+        begin
+          pc_o <= `ZeroWord;
+          pc_valid <= `InstInvalid;
+        end
+      else
+        begin
+          pc_o <= pc_i;
+          pc_valid <= `InstValid;
+        end
+    end
+
+endmodule
diff --git a/src/vsrc/pc2_reg.v b/src/vsrc/pc2_reg.v
diff --git a/src/vsrc/pipeline/1_fetch/if_id.v b/src/vsrc/pipeline/1_fetch/if_id.v
@@ -2,10 +2,11 @@
 module if_id (
     input wire clk,
     input wire rst,
-    
+
     input wire branch_flag_i,
     input wire[`InstAddrBus] if_pc_i,
     input wire[`InstAddrBus] if_inst_i,
+    input wire if_inst_valid,
     output reg[`InstAddrBus] id_pc_o,
     output reg[`InstBus] id_inst_o
   );
@@ -18,11 +19,11 @@ module if_id (
           id_pc_o <= `ZeroWord;
           id_inst_o <= `ZeroWord;
         end
-      else if(branch_flag_i)
-      begin
-        id_pc_o <= `ZeroWord;
-        id_inst_o <= `ZeroWord;
-      end
+      else if(branch_flag_i || if_inst_valid == `InstInvalid)
+        begin
+          id_pc_o <= `ZeroWord;
+          id_inst_o <= `ZeroWord;
+        end
       else
         begin
           id_inst_o <= if_inst_i;