Cpu toplevel, fetch-execute unit

eight_bit_console/eight_bit_console.cache/wt/project.wpc

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 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:7
+6d6f64655f636f756e7465727c4755494d6f6465:16
 eof:

eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 04/01/2024 11:14:34 AM
+// Design Name: 
+// Module Name: cpu
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module cpu(
+    input clk,
+    input [7:0] mem_data_in,
+    output [7:0] mem_data_out,
+    output [15:0] mem_addr,
+    output mem_read,
+    output mem_write
+    );
+
+    wire rfile_bit_mode;
+    wire rfile_we;
+    wire rfile_data_in;
+    wire rfile_data_in_wide;
+    wire rfile_write_sel;
+    wire rfile_sel_a;
+    wire rfile_sel_b;
+    wire rfile_output_a;
+    wire rfile_output_a_wide;
+    wire rfile_output_b;
+    wire rfile_output_b_wide;
+    wire rfile_flags_we;
+    wire rfile_new_flags;
+    wire rfile_cur_flags;
+
+
+    register_file rfile (
+        .clk(clk),
+        .wide_mode(rfile_bit_mode),
+        .we(rfile_we),
+        .data(rfile_data_in),
+        .data_wide(rfile_data_in_wide),
+        .dest_sel(rfile_write_sel),
+        .src_a_sel(rfile_sel_a),
+        .src_b_sel(rfile_sel_b),
+        .port_a(rfile_output_a),
+        .port_a_wide(rfile_output_a_wide),
+        .port_b(rfile_output_b),
+        .port_b_wide(rfile_output_b_wide),
+        .we_flags(rfile_flags_we),
+        .new_flags(rfile_new_flags),
+        .flags(rfile_cur_flags)
+    );
+
+
+    // Memory data bus logic
+    wire mem_select;
+
+
+
+    // Instruction pipeline and decoder
+    wire [15:0] fetcher_addr;
+    wire [7:0] fetcher_next_i;
+
+    wire [3:0] alu_function;
+    wire [11:0] reg_file_full_sel;
+    wire bit_mode;
+
+    fetch_execute executor_1 (
+        .clk(clk),
+        .mem_sel(mem_select),
+        .op_part_data(fetcher_next_i),
+        .op_part_addr(fetcher_addr),
+        .alu_sel(alu_function),
+        .reg_file_sel(reg_file_full_sel),
+        .bit_mode(bit_mode)
+    );
+
+
+
+endmodule
+

eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 04/02/2024 07:26:16 PM
+// Design Name:
+// Module Name: fetch_decode
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module fetch_execute(
+    input clk,
+    input [7:0] op_part_data,
+    output [15:0] op_part_addr,
+    output mem_sel,
+    output [3:0] alu_sel,
+    output [11:0] reg_file_sel,
+    output bit_mode
+    );
+
+    typedef logic [15:0] addr_t;
+
+    wire pc_enable;
+    wire pc_we;
+    wire pc_j_addr;
+    wire pc_cur_count;
+
+    program_counter prog_count (
+        .clk(clk),
+        .enable(pc_enable),
+        .we(pc_we),
+        .j_addr(pc_j_addr),
+        .count(pc_cur_count)
+    );
+
+
+    // Pipeline
+    byte op_part [3:0];
+    logic [3:0] dirty_pipe;
+
+    // Fetch logic
+    // addr_t cur_inst_addr = 0;
+
+    // Decode logic
+    logic [31:0] deco_op_parts = {op_part[0], op_part[1], op_part[2], op_part[3]};
+    logic [7:0] deco_cur_flags;
+    logic [3:1] deco_part_dirty;
+    logic deco_jump_en;
+    logic [15:0] deco_jump_addr;
+    logic instr_mem_access;
+    logic deco_pause_exec;
+    logic [7:0] deco_new_flags;
+
+    instruction_decoder inst_decode (
+        .op_parts(deco_op_parts),
+        .cur_flags(deco_cur_flags),
+        .cur_op_dirty(dirty_pipe[0]),
+        .part_dirty(deco_part_dirty),
+
+        // These are directly routed to the top level
+        .sel_reg(reg_file_sel),
+        .sel_alu(alu_sel),
+        .bit_mode(bit_mode),
+
+        .jump_en(deco_jump_en),
+        .jump_addr(deco_jump_addr),
+        .mem_access(instr_mem_access),
+        .pause_exec(deco_pause_exec),
+        .new_flags(deco_new_flags)
+    );
+
+
+    assign mem_sel = instr_mem_access;
+    assign op_part_addr = pc_cur_count;
+    assign pc_enable = !instr_mem_access;
+
+
+    always @(clk) begin
+        if (!instr_mem_access) begin
+            op_part[3] <= op_part_data;
+            op_part[2] <= op_part[3];
+            op_part[1] <= op_part[2];
+            op_part[0] <= op_part[1];
+        end
+
+    end
+
+endmodule