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Fix typo
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IsaacMarovitz committed Nov 28, 2023
1 parent 8a03fb5 commit 13b7491
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/cpu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ impl CPU {
fn alu_add(&mut self, x: u8) {
let a = self.reg.a;
let r = a.wrapping_add(x);
self.reg.set_flag(Flags::C, u16::from(a) + u16::from(x) > u16::from(u8::max));
self.reg.set_flag(Flags::C, u16::from(a) + u16::from(x) > u16::from(u8::MAX));
self.reg.set_flag(Flags::H, (a & 0x0F) + (a & 0x0F) > 0x0F);
self.reg.set_flag(Flags::N, false);
self.reg.set_flag(Flags::Z, r == 0x00);
Expand All @@ -136,7 +136,7 @@ impl CPU {
let a = self.reg.a;
let c = u8::from(self.reg.get_flag(Flags::C));
let r = a.wrapping_add(x).wrapping_add(c);
self.reg.set_flag(Flags::C, u16::from(a) + u16::from(x) + u16::from(c) > u16::from(u8::max));
self.reg.set_flag(Flags::C, u16::from(a) + u16::from(x) + u16::from(c) > u16::from(u8::MAX));
self.reg.set_flag(Flags::H, (a & 0x0F) + (a & 0x0F) + (c & 0x0F) > 0x0F);
self.reg.set_flag(Flags::N, false);
self.reg.set_flag(Flags::Z, r == 0x00);
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