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Boot ROM Fixes
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Fixed DMG, CGB still broken
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IsaacMarovitz committed Feb 2, 2024
1 parent f38b2b6 commit 63ceb7c
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Showing 3 changed files with 52 additions and 14 deletions.
13 changes: 7 additions & 6 deletions src/components/cpu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,25 +14,26 @@ pub struct CPU {
}

impl CPU {
pub fn new(mut rom: Vec<u8>, config: Config) -> Self {
pub fn new(rom: Vec<u8>, config: Config) -> Self {
let mut boot_rom: [u8; 0x900] = [0; 0x900];
let booting: bool = match config.boot_rom {
Some(ref path) => {
let mut boot_rom = Vec::new();
let mut boot_rom_vec = Vec::new();
let mut boot = match File::open(path.clone()) {
Ok(file) => file,
Err(err) => {
eprintln!("Failed to open Boot ROM at \"{}\": {}", path.clone(), err);
process::exit(1);
}
};
boot.read_to_end(&mut boot_rom)
boot.read_to_end(&mut boot_rom_vec)
.expect("Failed to read Boot ROM!");

// Copy Boot ROM
if config.mode == GBMode::DMG {
rom[0..=0x00FF].copy_from_slice(boot_rom.as_slice());
boot_rom[0..=0x00FF].copy_from_slice(boot_rom_vec.as_slice());
} else if config.mode == GBMode::CGB {
rom[0..=0x08FF].copy_from_slice(boot_rom.as_slice());
boot_rom[0..=0x08FF].copy_from_slice(boot_rom_vec.as_slice());
}

true
Expand All @@ -42,7 +43,7 @@ impl CPU {

Self {
reg: Registers::new(config.clone().mode, booting),
mem: MMU::new(rom, config),
mem: MMU::new(rom, config, booting, boot_rom),
halted: false,
ime: false,
ime_ask: false
Expand Down
50 changes: 43 additions & 7 deletions src/components/mmu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ pub struct MMU {
intf: Interrupts,
inte: Interrupts,
wram_bank: usize,
boot_rom: [u8; 0x900],
boot_rom_enabled: bool,
mode: GBMode
}

bitflags! {
Expand All @@ -31,9 +34,8 @@ bitflags! {
}

impl MMU {
pub fn new(rom: Vec<u8>, config: Config) -> Self {
let cart_type: CartTypes =
FromPrimitive::from_u8(rom[0x0147]).expect("Failed to get Cart Type!");
pub fn new(rom: Vec<u8>, config: Config, booting: bool, boot_rom: [u8; 0x900]) -> Self {
let cart_type: CartTypes = FromPrimitive::from_u8(rom[0x0147]).expect("Failed to get Cart Type!");
let mbc_mode = match cart_type.get_mbc() {
MBCMode::Unsupported => panic!("Unsupported Cart Type! {:}", cart_type),
v => {
Expand Down Expand Up @@ -64,6 +66,9 @@ impl MMU {
intf: Interrupts::empty(),
inte: Interrupts::empty(),
wram_bank: 0x01,
boot_rom,
boot_rom_enabled: booting,
mode: config.mode
}
}

Expand Down Expand Up @@ -99,8 +104,37 @@ impl MMU {
impl Memory for MMU {
fn read(&self, a: u16) -> u8 {
match a {
0x0000..=0x7FFF => self.mbc.read(a),
0x8000..=0x9FFF => self.ppu.read(a),
0x0000..=0x00FF => {
if self.boot_rom_enabled {
self.boot_rom[a as usize]
} else {
self.mbc.read(a)
}
}
0x0100..=0x1FFF => self.mbc.read(a),
0x0200..=0x7FFF => {
if self.mode == GBMode::DMG {
self.mbc.read(a)
} else {
if self.boot_rom_enabled {
self.boot_rom[a as usize]
} else {
self.mbc.read(a)
}
}
}
0x8000..=0x8FFF => {
if self.mode == GBMode::DMG {
self.ppu.read(a)
} else {
if self.boot_rom_enabled {
self.boot_rom[a as usize]
} else {
self.ppu.read(a)
}
}
}
0x9000..=0x9FFF => self.ppu.read(a),
0xA000..=0xBFFF => self.mbc.read(a),
0xC000..=0xCFFF => self.wram[a as usize - 0xC000],
0xD000..=0xDFFF => self.wram[a as usize - 0xD000 + 0x1000 * self.wram_bank],
Expand Down Expand Up @@ -141,15 +175,17 @@ impl Memory for MMU {
0xFF04..=0xFF07 => self.timer.write(a, v),
0xFF10..=0xFF3F => self.apu.write(a, v),
0xFF0F => self.intf = Interrupts::from_bits_truncate(v),
0xFF50..=0xFF5F => {}
0xFF50 => {
self.boot_rom_enabled = false;
}
0xFF51..=0xFF5F => {}
0xFF70 => {
self.wram_bank = match v & 0x07 {
0 => 1,
n => n as usize,
}
}
0xFEA0..=0xFEFF => {}
0xFF7F => {}
0xFFFF => self.inte = Interrupts::from_bits_truncate(v),
_ => panic!("Write to unsupported address ({:#06x})!", a),
}
Expand Down
3 changes: 2 additions & 1 deletion src/components/ppu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -617,7 +617,7 @@ impl Memory for PPU {
}
0xFF42 => self.sy = v,
0xFF43 => self.sx = v,
0xFF44 => print!("Attempted to write to LY!"),
0xFF44 => println!("Attempted to write to LY!"),
0xFF45 => {
self.lc = v;
self.check_lyc();
Expand All @@ -627,6 +627,7 @@ impl Memory for PPU {
0xFF49 => self.op1 = v,
0xFF4A => self.wy = v,
0xFF4B => self.wx = v,
0xFF4C => {}
// TODO: Handle PPU speed switching
0xFF4D => {}
0xFF4F => self.ram_bank = (v & 0x01) as usize,
Expand Down

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