16-bit LD

IsaacMarovitz · Dec 5, 2023 · a8016c0 · a8016c0
1 parent 0019347
commit a8016c0
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Showing 2 changed files with 23 additions and 0 deletions.
diff --git a/src/cpu.rs b/src/cpu.rs
@@ -25,10 +25,18 @@ impl CPU {
         byte
     }
 
+    pub fn read_word(&mut self) -> u16 {
+        let word = self.mem.read_word(self.reg.pc);
+        self.reg.pc += 2;
+        word
+    }
+
     pub fn call(&mut self) -> u32 {
         let opcode = self.read_byte();
         match opcode {
             0x00 => { 1 },
+            0x01 => { let v = self.read_word();
+                      self.reg.set_bc(v);                             3 },
             0x02 => { self.mem.write(self.reg.get_bc(), self.reg.a);  2 },
             0x03 => { let bc = self.reg.get_bc();
                       self.reg.set_bc(bc.wrapping_add(1));            2 },
@@ -41,6 +49,8 @@ impl CPU {
             0x0C => { self.reg.c = self.alu_inc(self.reg.c);          1 },
             0x0D => { self.reg.c = self.alu_dec(self.reg.c);          1 },
             0x0E => { self.reg.c = self.read_byte();                  2 },
+            0x11 => { let v = self.read_word();
+                      self.reg.set_de(v);                             3 },
             0x12 => { self.mem.write(self.reg.get_de(), self.reg.a);  2 },
             0x13 => { let de = self.reg.get_de();
                       self.reg.set_de(de.wrapping_add(1));            2 },
@@ -58,6 +68,8 @@ impl CPU {
                       { self.reg.pc += self.read_byte() as u16;       3 }
                       else { self.reg.pc += 1;                        2 }
                     },
+            0x21 => { let v = self.read_word();
+                      self.reg.set_hl(v);                             3 },
             0x22 => { let a = self.reg.get_hl();
                       self.mem.write(a, self.reg.a);
                       self.reg.set_hl(a + 1);                         2 },
@@ -82,6 +94,8 @@ impl CPU {
                       { self.reg.pc += self.read_byte() as u16;       3 }
                       else { self.reg.pc += 1;                        2 }
                     },
+            0x31 => { let v = self.read_word();
+                      self.reg.sp = v;                                3 },
             0x32 => { let a = self.reg.get_hl();
                       self.mem.write(a, self.reg.a);
                       self.reg.set_hl(a - 1);                         2 },

diff --git a/src/mmu.rs b/src/mmu.rs
@@ -34,4 +34,13 @@ impl MMU {
             _ => {},
         }
     }
+
+    pub fn read_word(&self, a: u16) -> u16 {
+        (self.read(a) as u16) | ((self.read(a + 1) as u16) << 8)
+    }
+
+    pub fn write_word(&mut self, a: u16, v: u16) {
+        self.write(a, (v & 0xFF) as u8);
+        self.write(a + 1, (v >> 8) as u8);
+    }
 }