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AND & XOR
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@IsaacMarovitz
IsaacMarovitz committed Nov 30, 2023
1 parent ef2a7a0 commit b360c49
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Showing 2 changed files with 59 additions and 14 deletions.
72 changes: 58 additions & 14 deletions src/cpu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,22 @@ impl CPU {
0x9D => { self.alu_sbc(self.reg.l); 1 },
0x9E => { self.alu_sbc(self.mem.read(self.reg.get_hl())); 2 },
0x9F => { self.alu_sbc(self.reg.a); 1 },
0xA0 => { self.alu_add(self.reg.b); 1 },
0xA1 => { self.alu_add(self.reg.c); 1 },
0xA2 => { self.alu_add(self.reg.d); 1 },
0xA3 => { self.alu_add(self.reg.e); 1 },
0xA4 => { self.alu_add(self.reg.h); 1 },
0xA5 => { self.alu_add(self.reg.l); 1 },
0xA6 => { self.alu_add(self.mem.read(self.reg.get_hl())); 2 },
0xA7 => { self.alu_add(self.reg.a); 1 },
0xA8 => { self.alu_xor(self.reg.b); 1 },
0xA9 => { self.alu_xor(self.reg.c); 1 },
0xAA => { self.alu_xor(self.reg.d); 1 },
0xAB => { self.alu_xor(self.reg.e); 1 },
0xAC => { self.alu_xor(self.reg.h); 1 },
0xAD => { self.alu_xor(self.reg.l); 1 },
0xAE => { self.alu_xor(self.mem.read(self.reg.get_hl())); 2 },
0xAF => { self.alu_xor(self.reg.a); 1 },
0xCB => { self.cb_call() },
// Should be a panic!, keep it as a println! for now
code => { println!("Instruction {:} is unknown!", code); 0 },
Expand All @@ -164,69 +180,77 @@ impl CPU {
pub fn cb_call(&mut self) -> u32 {
let opcode = self.read_byte();
match opcode {
0x40 => { self.alu_bit(self.reg.b, 0); 2 },
0x41 => { self.alu_bit(self.reg.c, 0); 2 },
0x42 => { self.alu_bit(self.reg.d, 0); 2 },
0x43 => { self.alu_bit(self.reg.e, 0); 2 },
0x44 => { self.alu_bit(self.reg.h, 0); 2 },
0x45 => { self.alu_bit(self.reg.l, 0); 2 },
0x46 => { 4 }, // BIT 0, HL
0x40 => { self.alu_bit(self.reg.b, 0); 2 },
0x41 => { self.alu_bit(self.reg.c, 0); 2 },
0x42 => { self.alu_bit(self.reg.d, 0); 2 },
0x43 => { self.alu_bit(self.reg.e, 0); 2 },
0x44 => { self.alu_bit(self.reg.h, 0); 2 },
0x45 => { self.alu_bit(self.reg.l, 0); 2 },
0x46 => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 0); 4 },
0x47 => { self.alu_bit(self.reg.a, 0); 2 },
0x48 => { self.alu_bit(self.reg.b, 1); 2 },
0x49 => { self.alu_bit(self.reg.c, 1); 2 },
0x4A => { self.alu_bit(self.reg.d, 1); 2 },
0x4B => { self.alu_bit(self.reg.e, 1); 2 },
0x4C => { self.alu_bit(self.reg.h, 1); 2 },
0x4D => { self.alu_bit(self.reg.l, 1); 2 },
0x4E => { 4 }, // BIT 1, HL
0x4E => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 1); 4 },
0x4F => { self.alu_bit(self.reg.a, 1); 2 },
0x50 => { self.alu_bit(self.reg.b, 2); 2 },
0x51 => { self.alu_bit(self.reg.c, 2); 2 },
0x52 => { self.alu_bit(self.reg.d, 2); 2 },
0x53 => { self.alu_bit(self.reg.e, 2); 2 },
0x54 => { self.alu_bit(self.reg.h, 2); 2 },
0x55 => { self.alu_bit(self.reg.l, 2); 2 },
0x56 => { 4 }, // BIT 2, HL
0x56 => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 2); 4 },
0x57 => { self.alu_bit(self.reg.a, 2); 2 },
0x58 => { self.alu_bit(self.reg.b, 3); 2 },
0x59 => { self.alu_bit(self.reg.c, 3); 2 },
0x5A => { self.alu_bit(self.reg.d, 3); 2 },
0x5B => { self.alu_bit(self.reg.e, 3); 2 },
0x5C => { self.alu_bit(self.reg.h, 3); 2 },
0x5D => { self.alu_bit(self.reg.l, 3); 2 },
0x5E => { 4 }, // BIT 3, HL
0x5E => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 3); 4 },
0x5F => { self.alu_bit(self.reg.a, 3); 2 },
0x60 => { self.alu_bit(self.reg.b, 4); 2 },
0x61 => { self.alu_bit(self.reg.c, 4); 2 },
0x62 => { self.alu_bit(self.reg.d, 4); 2 },
0x63 => { self.alu_bit(self.reg.e, 4); 2 },
0x64 => { self.alu_bit(self.reg.h, 4); 2 },
0x65 => { self.alu_bit(self.reg.l, 4); 2 },
0x66 => { 4 }, // BIT 4, HL
0x66 => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 4); 4 },
0x67 => { self.alu_bit(self.reg.a, 4); 2 },
0x68 => { self.alu_bit(self.reg.b, 5); 2 },
0x69 => { self.alu_bit(self.reg.c, 5); 2 },
0x6A => { self.alu_bit(self.reg.d, 5); 2 },
0x6B => { self.alu_bit(self.reg.e, 5); 2 },
0x6C => { self.alu_bit(self.reg.h, 5); 2 },
0x6D => { self.alu_bit(self.reg.l, 5); 2 },
0x6E => { 4 }, // BIT 5, HL
0x6E => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 5); 4 },
0x6F => { self.alu_bit(self.reg.a, 5); 2 },
0x70 => { self.alu_bit(self.reg.b, 6); 2 },
0x71 => { self.alu_bit(self.reg.c, 6); 2 },
0x72 => { self.alu_bit(self.reg.d, 6); 2 },
0x73 => { self.alu_bit(self.reg.e, 6); 2 },
0x74 => { self.alu_bit(self.reg.h, 6); 2 },
0x75 => { self.alu_bit(self.reg.l, 6); 2 },
0x76 => { 4 }, // BIT 6, HL
0x76 => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 6); 4 },
0x77 => { self.alu_bit(self.reg.a, 6); 2 },
0x78 => { self.alu_bit(self.reg.b, 7); 2 },
0x79 => { self.alu_bit(self.reg.c, 7); 2 },
0x7A => { self.alu_bit(self.reg.d, 7); 2 },
0x7B => { self.alu_bit(self.reg.e, 7); 2 },
0x7C => { self.alu_bit(self.reg.h, 7); 2 },
0x7D => { self.alu_bit(self.reg.l, 7); 2 },
0x7E => { 4 }, // BIT 7, HL
0x7E => { let a = self.reg.get_hl();
self.alu_bit(self.mem.read(a), 7); 4 },
0x7F => { self.alu_bit(self.reg.a, 7); 2 },
// Should be a panic!, keep it as a println! for now
code => { println!("CB Instruction {:2X} is unknown!", code); 0 },
Expand Down Expand Up @@ -275,6 +299,26 @@ impl CPU {
self.reg.a = r;
}

fn alu_and(&mut self, x: u8) {
let a = self.reg.a;
let r = a & x;
self.reg.set_flag(Flags::C, false);
self.reg.set_flag(Flags::H, true);
self.reg.set_flag(Flags::N, false);
self.reg.set_flag(Flags::Z, r == 0);
self.reg.a = r;
}

fn alu_xor(&mut self, x: u8) {
let a = self.reg.a;
let r = a ^ x;
self.reg.set_flag(Flags::C, false);
self.reg.set_flag(Flags::H, false);
self.reg.set_flag(Flags::N, false);
self.reg.set_flag(Flags::Z, r == 0);
self.reg.a = r;
}

fn alu_bit(&mut self, a: u8, b: u8) {
let r = a & (1 << b) == 0x00;
self.reg.set_flag(Flags::H, true);
Expand Down
1 change: 1 addition & 0 deletions src/mmu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ impl MMU {

pub fn write(&mut self, a: u16, v: u8) {
match a {
0x0000..=0x8000 => self.rom[a as usize] = v,
0xC000..=0xCFFF => self.wram[a as usize - 0xC000] = v,
0xFF80..=0xFFFE => self.hram[a as usize - 0xFF80] = v,
0xFFFF => self.interrupt = v,
Expand Down

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