Skip to content

Commit

Permalink
feat(DataCheck): support dummy DataCheck and Poison (OpenXiangShan#19)
Browse files Browse the repository at this point in the history
* feat(DataCheck): support dummy DataCheck and Poison

* Enabled DataCheck of CoupledL2 in TestTop.

* submodule(CoupledL2): bump CoupledL2
  • Loading branch information
Kumonda221-CrO3 authored Dec 4, 2024
1 parent a1561e1 commit a6748e3
Show file tree
Hide file tree
Showing 3 changed files with 6 additions and 1 deletion.
2 changes: 1 addition & 1 deletion coupledL2
Submodule coupledL2 updated 44 files
+31 −34 Makefile
+1 −1 rocket-chip
+2 −3 src/main/scala/coupledL2/BaseSlice.scala
+20 −16 src/main/scala/coupledL2/Common.scala
+59 −23 src/main/scala/coupledL2/CoupledL2.scala
+55 −5 src/main/scala/coupledL2/DataStorage.scala
+54 −16 src/main/scala/coupledL2/Directory.scala
+2 −2 src/main/scala/coupledL2/GrantBuffer.scala
+13 −3 src/main/scala/coupledL2/L2Param.scala
+16 −15 src/main/scala/coupledL2/RequestArb.scala
+10 −1 src/main/scala/coupledL2/RequestBuffer.scala
+6 −2 src/main/scala/coupledL2/SinkA.scala
+3 −0 src/main/scala/coupledL2/SinkC.scala
+0 −74 src/main/scala/coupledL2/SinkCMO.scala
+17 −13 src/main/scala/coupledL2/TopDownMonitor.scala
+56 −28 src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+5 −2 src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala
+53 −2 src/main/scala/coupledL2/prefetch/Prefetcher.scala
+12 −1 src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala
+7 −3 src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
+199 −89 src/main/scala/coupledL2/tl2chi/MSHR.scala
+26 −5 src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
+107 −58 src/main/scala/coupledL2/tl2chi/MainPipe.scala
+18 −0 src/main/scala/coupledL2/tl2chi/RXDAT.scala
+1 −0 src/main/scala/coupledL2/tl2chi/RXRSP.scala
+17 −4 src/main/scala/coupledL2/tl2chi/RXSNP.scala
+7 −5 src/main/scala/coupledL2/tl2chi/Slice.scala
+1 −1 src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
+21 −1 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+3 −0 src/main/scala/coupledL2/tl2chi/TXREQ.scala
+5 −1 src/main/scala/coupledL2/tl2chi/TXRSP.scala
+12 −4 src/main/scala/coupledL2/tl2chi/chi/CHILogger.scala
+12 −11 src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala
+138 −0 src/main/scala/coupledL2/tl2chi/chi/Message.scala
+13 −0 src/main/scala/coupledL2/tl2tl/MSHR.scala
+26 −1 src/main/scala/coupledL2/tl2tl/MSHRCtl.scala
+60 −9 src/main/scala/coupledL2/tl2tl/MainPipe.scala
+1 −0 src/main/scala/coupledL2/tl2tl/RefillUnit.scala
+0 −1 src/main/scala/coupledL2/tl2tl/SinkB.scala
+7 −3 src/main/scala/coupledL2/tl2tl/Slice.scala
+8 −0 src/main/scala/coupledL2/utils/Replacer.scala
+18 −3 src/test/scala/TestTop.scala
+107 −174 src/test/scala/chi/TestTop.scala
+1 −1 utility
2 changes: 2 additions & 0 deletions src/main/scala/openLLC/Common.scala
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,8 @@ class TaskWithData(implicit p: Parameters) extends LLCBundle {
dat.be := Fill(BE_WIDTH, true.B)
dat.data := data.data(beatId).data
dat.dataID := (beatBytes * beatId * 8).U(log2Ceil(blockBytes * 8) - 1, log2Ceil(blockBytes * 8) - 2)
dat.dataCheck := Cat((0 until DATACHECK_WIDTH).map(i => data.data(beatId).data(8 * (i + 1) - 1, 8 * i).xorR.asUInt))
dat.poision := 0.U
dat
}
}
Expand Down
3 changes: 3 additions & 0 deletions src/test/scala/TestTop.scala
Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,9 @@ object TestTopSoCHelper {
elaboratedTopDown = false,
FPGAPlatform = FPGAPlatform,

// OddParity Data Check
dataCheck = Some("oddparity"),

// SAM for tester ICN: Home Node ID = 33
sam = Seq(AddressSet.everything -> 33)
)
Expand Down

0 comments on commit a6748e3

Please sign in to comment.