Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.
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The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.
The processor was implemented using SystemVerilog.
Grande RISCO 5 currently supports the following RISC-V extensions:
| Extension | Support |
|---|---|
| I | Complete |
| M | Complete |
| C | Complete |
| B | In progress |
| A | Speculative |
| Zicsr | In progress |
The Verification_tests directory contains examples and tests written in Assembly, along with their respective memory files. Additionally, there is a script available to convert Assembly into memory files (.hex).
The Testbenchs directory contains testbenches developed using Icarus Verilog (Iverilog). Most tests are compatible with Iverilog, and some have been ported to Verilator.
Grande RISCO 5 is part of a family of RISC-V processors developed for different purposes:
- Baby Risco 5 - RV32E, optimized for TinyTapeout.
- Pequeno Risco 5 - RV32I, single-cycle implementation (Archived).
- Risco 5 - RV32I/E[M], multi-cycle implementation (Paused).
- Grande Risco 5 - RV32I, pipeline implementation.
- Risco 5 Bodybuilder - RV64IMA, still speculative.
- RISCO 5S - RV32IM, simulator written in C.
The official documentation is available at: jn513.github.io/Grande-Risco-5. If you have any questions or suggestions, feel free to use the ISSUES section on GitHub. Contributions are welcome, and all Pull Requests will be reviewed.
If you wish to contribute to the project, follow the instructions in the CONTRIBUTING.md file.
This project is licensed under CERN-OHL-P-2.0, ensuring full usage freedom.
- The software is under the MIT License.
- The documentation follows CC BY-SA 4.0.
Logo author: Mateus Luck