This repository contains the files for labs related to ECSE 222 - Digital Logic at McGill University.
The labs were created using the Intel Quartus development environment, ensuring compatibility and seamless integration with Altera FPGAs. For simulation purposes, ModelSim was employed to rigorously test and validate the VHDL code.
To provide a real-world simulation experience, the VHDL code has been mapped, flashed, and tested onto the Altera DE1-SoC Board. This allowed for the exploration of the functionality of the digital logic circuits in a hardware environment, providing practical insights beyond mere software simulation.