This project is part of National University of Singapore's EE2026 Digital Design, using Verilog HDL to program a FPGA (Digilent Basys3)
More in the user guide.
The project is designed to promote healthy sleep habits by assisting the user throughout their sleep journey, from the moment they decide to go to bed until they wake up.
Main Menu: To select a game or function, press "btnC." To return to the main menu, press "btnC" again. Navigate through the menu options by pressing the “btnL” or"btnR" button to move to the next game or function. To reset a game, press "btnD."
Features and Functions
- Determine if the environment is suitable for sleep
- Play a game to unwind before sleeping
- Set an alarm that rings
- Unlock the system with a password to wake up properly
The overall group improvement is the menu selection. We have improved the user experience by enhancing the menu selection for choosing different games and feature
AudioInput module - NUS
AudioOut module - NUS
COE Generator - https://github.com/kooltzh/xilinx-coe-generator
XADC Demo - Digilent https://digilent.com/reference/programmable-logic/basys-3/demos/xadc
- User Guide
- Main Project
- Pre-Project Basic Tasks
- Lab 1-3