A 32-bit pipelined risc-v softcore processor in verilog. This directory contains the files to build the core and tests to run some basic ASM test programs.
**Primarily done as a side project**.
Written based on the book:
[Digital Logic Design: Risc-V Edition](https://www.amazon.com/Digital-Design-Computer-Architecture-RISC-V/dp/0128200642)