Skip to content

Commit

Permalink
Fixed issue #1594 (#1596)
Browse files Browse the repository at this point in the history
Co-authored-by: Matthias Koefferlein <[email protected]>
  • Loading branch information
klayoutmatthias and Matthias Koefferlein authored Feb 11, 2024
1 parent 8d4da8b commit 3ab442b
Show file tree
Hide file tree
Showing 5 changed files with 58 additions and 1 deletion.
3 changes: 2 additions & 1 deletion src/drc/drc/built-in-macros/_drc_netter.rb
Original file line number Diff line number Diff line change
Expand Up @@ -702,7 +702,8 @@ def _make_data
@l2n = RBA::LayoutToNetlist::new(@engine._dss)
else
layout = @engine.source.layout
@l2n = RBA::LayoutToNetlist::new(layout.top_cell.name, layout.dbu)
cell_name = @engine.source.cell_name
@l2n = RBA::LayoutToNetlist::new(cell_name, layout.dbu)
end

@l2n.name = "DRC"
Expand Down
36 changes: 36 additions & 0 deletions src/drc/unit_tests/drcSimpleTests.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1617,3 +1617,39 @@ TEST(89_deep_with_mag_cop_size_aniso)
run_test (_this, "89", true);
}

TEST(90_issue1594_dual_top)
{
std::string rs = tl::testdata ();
rs += "/drc/issue_1594.drc";

std::string input = tl::testdata ();
input += "/drc/issue_1594.gds";

std::string au = tl::testdata ();
au += "/drc/issue_1594_au.cir";

std::string output = this->tmp_file ("tmp.cir");

{
// Set some variables
lym::Macro config;
config.set_text (tl::sprintf (
"$drc_force_gc = true\n"
"$drc_test_source = '%s'\n"
"$drc_test_target = '%s'\n"
, input, output)
);
config.set_interpreter (lym::Macro::Ruby);
EXPECT_EQ (config.run (), 0);
}

lym::Macro drc;
drc.load_from (rs);
EXPECT_EQ (drc.run (), 0);

// verify

CHECKPOINT ();
compare_netlists (_this, output, au);
}

15 changes: 15 additions & 0 deletions testdata/drc/issue_1594.drc
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
source($drc_test_source, "TOP1")

# This is just a smoke test without actual devices

l1 = input(1, 0)
l2 = input(2, 0)
l3 = input(3, 0)

connect(l1, l2)
connect(l2, l3)

writer = RBA::NetlistSpiceWriter::new

netlist.write($drc_test_target, writer, "netlist")

Binary file added testdata/drc/issue_1594.gds
Binary file not shown.
5 changes: 5 additions & 0 deletions testdata/drc/issue_1594_au.cir
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
* netlist

* cell TOP1
.SUBCKT TOP1
.ENDS TOP1

0 comments on commit 3ab442b

Please sign in to comment.