Fix all verilator warnings

deepsocflow/py/hardware.py

@@ -198,7 +198,7 @@ def simulate(self, SIM='verilator', SIM_PATH=''):
             assert subprocess.run(cmd).returncode == 0
 
         if SIM == "verilator":
-            cmd = f'{SIM_PATH}verilator --binary -j 0 -Wno-fatal -Wno-WIDTHEXPAND --trace --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -I../ {self.MODULE_DIR}/c/example.c --Mdir ./'
+            cmd = f'{SIM_PATH}verilator --binary -j 0 --trace --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -I../ {self.MODULE_DIR}/c/example.c --Mdir ./'
             print(cmd)
             assert subprocess.run(cmd.split(' '), cwd='build').returncode == 0
 

deepsocflow/rtl/axis_pixels.sv

@@ -192,7 +192,7 @@ module axis_pixels #(
 
   always_comb
     for (int r=0; r<ROWS; r=r+1)
-      m_data[r] = shift_reg[r + EDGE_WORDS-ref_kh2];
+      m_data[r] = shift_reg[r + EDGE_WORDS-32'(ref_kh2)];
 
   // m_valid, m_last
 

deepsocflow/rtl/axis_weight_rotator.sv

@@ -64,8 +64,8 @@ module axis_weight_rotator #(
     logic [BITS_ADDR        -1:0] addr_max;
     logic [BITS_XN          -1:0] xn_1;
     logic [BITS_IM_BLOCKS   -1:0] blocks_1;
-    logic [BITS_XW     -1:0] cols_1;
-    logic [BITS_CI      -1:0] cin_1;
+    logic [BITS_XW          -1:0] cols_1;
+    logic [BITS_CI          -1:0] cin_1;
     logic [BITS_KW2         -1:0] kw2;
   } config_st;
   config_st s_config, count;
@@ -327,7 +327,7 @@ module axis_weight_rotator #(
   assign m_axis_tuser.kw2              = ref_i_read.kw2;
   assign m_axis_tuser.is_w_first_clk   = f_cols && f_cin && f_kw;
   assign m_axis_tuser.is_cin_last      = l_kw   && l_cin;
-  assign m_axis_tuser.is_w_first_kw2   = (ref_i_read.cols_1 - c_cols) < ref_i_read.kw2;
+  assign m_axis_tuser.is_w_first_kw2   = (ref_i_read.cols_1 - c_cols) < BITS_XW'(ref_i_read.kw2);
   assign m_axis_tuser.is_w_last        = l_cols;
 
 endmodule

deepsocflow/rtl/dnn_engine.v

@@ -125,12 +125,15 @@ module dnn_engine #(
   );
 
   localparam Y_BITS_PADDED = 2**$clog2(Y_BITS);
+  localparam Y_PADDING     = Y_BITS_PADDED-Y_BITS;
   genvar iy;
 
   wire [Y_BITS_PADDED*ROWS-1:0] m_data_padded;
   generate
     for (iy=0; iy<ROWS; iy=iy+1) begin
-      assign m_data_padded[Y_BITS_PADDED*(iy+1)-1:Y_BITS_PADDED*iy] = $signed(m_data[Y_BITS*(iy+1)-1:Y_BITS*iy]);
+      // Sign padding: can be done as $signed(), but verilator gives warning for width mismatch
+      wire sign_bit = m_data[Y_BITS*(iy+1)-1];
+      assign m_data_padded[Y_BITS_PADDED*(iy+1)-1:Y_BITS_PADDED*iy] = {{Y_PADDING{sign_bit}}, m_data[Y_BITS*(iy+1)-1:Y_BITS*iy]};
     end
   endgenerate
 

deepsocflow/rtl/ext/alex_axis_adapter.sv

@@ -120,8 +120,8 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
     // data width and keep width per segment
     localparam SEG_DATA_WIDTH = M_DATA_WIDTH / SEG_COUNT;
     localparam SEG_KEEP_WIDTH = M_BYTE_LANES / SEG_COUNT;
-
-    reg [$clog2(SEG_COUNT)-1:0] seg_reg = 0;
+    localparam BITS_SEG_REG = $clog2(SEG_COUNT);
+    reg [BITS_SEG_REG-1:0] seg_reg = 0;
 
     reg [S_DATA_WIDTH-1:0] s_axis_tdata_reg;
     reg [S_KEEP_WIDTH-1:0] s_axis_tkeep_reg;
@@ -157,7 +157,7 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
 
             if (seg_reg == 0) begin
                 m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tvalid_reg ? s_axis_tdata_reg : s_axis_tdata;
-                m_axis_tkeep_reg <= s_axis_tvalid_reg ? s_axis_tkeep_reg : s_axis_tkeep;
+                m_axis_tkeep_reg <= s_axis_tvalid_reg ? M_KEEP_WIDTH'(s_axis_tkeep_reg) : M_KEEP_WIDTH'(s_axis_tkeep);
             end else begin
                 m_axis_tdata_reg[seg_reg*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] <= s_axis_tdata;
                 m_axis_tkeep_reg[seg_reg*SEG_KEEP_WIDTH +: SEG_KEEP_WIDTH] <= s_axis_tkeep;
@@ -171,15 +171,15 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize
                 // consume data from buffer
                 s_axis_tvalid_reg <= 1'b0;
 
-                if (s_axis_tlast_reg || seg_reg == SEG_COUNT-1) begin
+                if (s_axis_tlast_reg || seg_reg == BITS_SEG_REG'(SEG_COUNT-1)) begin
                     seg_reg <= 0;
                     m_axis_tvalid_reg <= 1'b1;
                 end else begin
                     seg_reg <= seg_reg + 1;
                 end
             end else if (s_axis_tvalid) begin
                 // data direct from input
-                if (s_axis_tlast || seg_reg == SEG_COUNT-1) begin
+                if (s_axis_tlast || seg_reg == BITS_SEG_REG'(SEG_COUNT-1)) begin
                     seg_reg <= 0;
                     m_axis_tvalid_reg <= 1'b1;
                 end else begin

deepsocflow/test/sv/counter_tb.sv

@@ -1,3 +1,4 @@
+`timescale 1ns/1ps
 
 module counter_tb;
   localparam W = 8;

deepsocflow/test/sv/dma.sv

@@ -33,7 +33,7 @@ module DMA_M2S #(
     while (~prev_slast) begin    // loop goes from (aresetn & s_ready) to s_last
       if (prev_handshake) begin  // change data
         for (int i=0; i < BYTES_PER_BEAT; i++) begin
-          if(i_bytes >= bytes_per_transfer) begin
+          if(i_bytes >= 64'(bytes_per_transfer)) begin
             s_data_val[i] = 0;
             s_keep_val[i] = 0;
           end
@@ -43,7 +43,7 @@ module DMA_M2S #(
             s_keep_val[i] = 1;
             i_bytes  += 1;
           end
-          s_last_val = i_bytes >= bytes_per_transfer;
+          s_last_val = i_bytes >= 64'(bytes_per_transfer);
         end
       end
       s_valid = $urandom_range(0,999) < PROB_VALID;      // randomize s_valid

deepsocflow/test/sv/dnn_engine_tb.sv

@@ -104,9 +104,9 @@ module dnn_engine_tb;
 
     fill_memory(w_base, x_base);
 
-    for (int i=0; i<50; i++)
+    for (longint i=0; i<50; i++)
       $display("weights: i:%h, w:%b", i, get_byte(w_base + i));
-    for (int i=0; i<10; i++)
+    for (longint i=0; i<10; i++)
       $display("inputs : i:%h, w:%b", i, get_byte(x_base + i));
 
     repeat(2) @(posedge aclk) #1;