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fix stuck.py issue
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awengz committed Aug 2, 2024
1 parent 3645ce1 commit 28004ef
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49 changes: 33 additions & 16 deletions deepsocflow/rtl/proc_engine.sv
Original file line number Diff line number Diff line change
Expand Up @@ -231,33 +231,50 @@ endgenerate

//assign cnt_en = m_ready & ~shift_out_ready[COLS-1] & (outshift_flag[COLS-1-count_outshift] == 1);

for (co=0; co<COLS; co=co+1) begin : Cs

// outshift_flag is used to decide whether the column should be shifted out or not
// outshift_flag is set to 1 for all cols when the last col of out shifter gets valid data
// it is set to 0 when shift_out_ready[co] = 0 i.e. the data from that col has been shifted out.
always_ff@(posedge clk `OR_NEGEDGE(resetn)) begin
always_ff@(posedge clk `OR_NEGEDGE(resetn)) begin
if (!resetn) begin
outshift_flag[co] <= 0;
outshift_flag <= 0;
end
else begin
if (co == COLS-1) shift_out_ready_last_col_prev <= shift_out_ready[COLS-1];
shift_out_ready_last_col_prev <= shift_out_ready[COLS-1];

if(shift_out_ready_last_col_prev & ~shift_out_ready[COLS-1]) begin // when last col of out shifter gets data from acc, it is ready to start shifting.
outshift_flag[co] <= 1;
outshift_flag <= '1;
end
else begin
//else if ((count_outshift == (COLS-1)-co) && en_outshift[co]) begin
if (co < COLS-1) begin
if (shift_out_ready[co]) begin
outshift_flag[co] <= 0;
end
end
else if (shift_out_ready[co]) outshift_flag[co] <= 0; // for last column

if (m_ready && ~shift_out_ready[COLS-1]) outshift_flag <= (outshift_flag << 1);
end
end
end

for (co=0; co<COLS; co=co+1) begin : Cs

// outshift_flag is used to decide whether the column should be shifted out or not
// outshift_flag is set to 1 for all cols when the last col of out shifter gets valid data
// it is set to 0 when shift_out_ready[co] = 0 i.e. the data from that col has been shifted out.
// always_ff@(posedge clk `OR_NEGEDGE(resetn)) begin
// if (!resetn) begin
// outshift_flag[co] <= 0;
// end
// else begin
// if (co == COLS-1) shift_out_ready_last_col_prev <= shift_out_ready[COLS-1];

// if(shift_out_ready_last_col_prev & ~shift_out_ready[COLS-1]) begin // when last col of out shifter gets data from acc, it is ready to start shifting.
// outshift_flag[co] <= 1;
// end
// else begin
// //else if ((count_outshift == (COLS-1)-co) && en_outshift[co]) begin
// if (co < COLS-1) begin
// if (shift_out_ready[co]) begin
// outshift_flag[co] <= 0;
// end
// end
// else if (shift_out_ready[co]) outshift_flag[co] <= 0; // for last column

// end
// end
// end

// en_outshift enables the output shifter register. The first condition is to shift data out,
// and the second condition is for the accumulator to write to the output shifter.
Expand Down
2 changes: 1 addition & 1 deletion deepsocflow/test/sv/axi_sys_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ module axi_sys_tb;
$dumpfile("axi_tb_sys.vcd");
$dumpvars();
#2000us;
$finish;
//$finish;
end

chandle mpv, cp;
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4 changes: 2 additions & 2 deletions run/param_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@

from deepsocflow import *

(SIM, SIM_PATH) = ('xsim', "F:/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
(SIM, SIM_PATH) = ('xsim', "E:/Vivado/2023.2/bin/") if os.name=='nt' else ('verilator', '')

'''
Dataset
Expand Down Expand Up @@ -217,4 +217,4 @@ def test_dnn_engine(PARAMS):
d_perf = predict_model_performance(hw)
pp = pprint.PrettyPrinter(indent=4)
print(f"Predicted Performance")
pp.pprint(d_perf)
pp.pprint(d_perf)
2 changes: 1 addition & 1 deletion run/stuck.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@

from deepsocflow import *

(SIM, SIM_PATH) = ('xsim', "F:/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
(SIM, SIM_PATH) = ('xsim', "E:/Vivado/2023.2/bin/") if os.name=='nt' else ('verilator', '')


input_shape = (14,14,256)
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40 changes: 19 additions & 21 deletions run/work/config_fw.h
Original file line number Diff line number Diff line change
@@ -1,34 +1,32 @@
#define N_BUNDLES 7
#define N_BUNDLES 5
Bundle_t bundles [N_BUNDLES] = {
{.n=1 , .l=4 , .kw=7 , .coe=3 , .h=28 , .w=28 , .ci=1 , .co=8 , .w_kw2=25 , .t=3 , .p=1 , .cm=2 , .cm_p0=1 , .on=1 , .oh=7 , .ow=10 , .oc=8 , .ch=14 , .ph=7 , .cw=28 , .pw=10 , .xp_words=1344 , .b_offset=0 , .w_bpt=84 , .w_bpt_p0=84 , .x_bpt=672 , .x_bpt_p0=672 , .o_words=640 , .o_bytes=320 , .ib_out=1 , .in_buffer_idx=-1 , .out_buffer_idx=0 , .add_out_buffer_idx=0 , .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=4 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=0 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=1 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=2 , .csh_shift=1 , .pkh=3 , .psh=2 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=4 , .psw=3 , .psw_shift=1 , .pool=POOL_AVG , .softmax_max_f=0 , .header= 29695610579857627u, .debug_nhwc_words=560 },
{.n=1 , .l=1 , .kw=1 , .coe=24 , .h=7 , .w=10 , .ci=8 , .co=8 , .w_kw2=10 , .t=1 , .p=1 , .cm=20 , .cm_p0=8 , .on=1 , .oh=7 , .ow=10 , .oc=8 , .ch=7 , .ph=7 , .cw=10 , .pw=10 , .xp_words=80 , .b_offset=9 , .w_bpt=96 , .w_bpt_p0=96 , .x_bpt=320 , .x_bpt_p0=320 , .o_words=960 , .o_bytes=480 , .ib_out=2 , .in_buffer_idx=0 , .out_buffer_idx=1 , .add_out_buffer_idx=1 , .add_in_buffer_idx=0 , .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=1 , .aa_shift=3 , .aa_pl_scale=3 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 43276787871645768u, .debug_nhwc_words=560 },
{.n=1 , .l=1 , .kw=7 , .coe=3 , .h=7 , .w=10 , .ci=8 , .co=8 , .w_kw2=7 , .t=3 , .p=4 , .cm=2 , .cm_p0=2 , .on=1 , .oh=7 , .ow=10 , .oc=8 , .ch=7 , .ph=7 , .cw=10 , .pw=10 , .xp_words=120 , .b_offset=33 , .w_bpt=168 , .w_bpt_p0=168 , .x_bpt=120 , .x_bpt_p0=120 , .o_words=960 , .o_bytes=480 , .ib_out=3 , .in_buffer_idx=1 , .out_buffer_idx=0 , .add_out_buffer_idx=-1, .add_in_buffer_idx=1 , .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=4 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 30188191789350987u, .debug_nhwc_words=560 },
{.n=1 , .l=1 , .kw=5 , .coe=4 , .h=7 , .w=10 , .ci=8 , .co=8 , .w_kw2=8 , .t=2 , .p=2 , .cm=4 , .cm_p0=4 , .on=1 , .oh=7 , .ow=10 , .oc=8 , .ch=7 , .ph=7 , .cw=10 , .pw=10 , .xp_words=120 , .b_offset=42 , .w_bpt=240 , .w_bpt_p0=240 , .x_bpt=240 , .x_bpt_p0=240 , .o_words=960 , .o_bytes=480 , .ib_out=4 , .in_buffer_idx=0 , .out_buffer_idx=1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=0 , .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=4 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 44121204210794570u, .debug_nhwc_words=560 },
{.n=1 , .l=1 , .kw=3 , .coe=8 , .h=7 , .w=10 , .ci=8 , .co=24 , .w_kw2=9 , .t=3 , .p=2 , .cm=6 , .cm_p0=2 , .on=1 , .oh=7 , .ow=10 , .oc=24 , .ch=7 , .ph=7 , .cw=10 , .pw=10 , .xp_words=120 , .b_offset=50 , .w_bpt=216 , .w_bpt_p0=72 , .x_bpt=360 , .x_bpt_p0=120 , .o_words=1920 , .o_bytes=960 , .ib_out=5 , .in_buffer_idx=1 , .out_buffer_idx=0 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=4 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=0 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 38632443238154313u, .debug_nhwc_words=1680 },
{.n=1 , .l=1 , .kw=1 , .coe=24 , .h=7 , .w=10 , .ci=24 , .co=10 , .w_kw2=10 , .t=1 , .p=2 , .cm=20 , .cm_p0=4 , .on=1 , .oh=1 , .ow=1 , .oc=700 , .ch=7 , .ph=7 , .cw=10 , .pw=10 , .xp_words=80 , .b_offset=74 , .w_bpt=240 , .w_bpt_p0=48 , .x_bpt=800 , .x_bpt_p0=160 , .o_words=5600 , .o_bytes=2800 , .ib_out=6 , .in_buffer_idx=0 , .out_buffer_idx=1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=1 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=0 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 42995312893886536u, .debug_nhwc_words=700 },
{.n=1 , .l=1 , .kw=1 , .coe=24 , .h=1 , .w=1 , .ci=700 , .co=10 , .w_kw2=1 , .t=1 , .p=35 , .cm=20 , .cm_p0=20 , .on=1 , .oh=1 , .ow=1 , .oc=10 , .ch=1 , .ph=1 , .cw=1 , .pw=1 , .xp_words=8 , .b_offset=98 , .w_bpt=240 , .w_bpt_p0=240 , .x_bpt=80 , .x_bpt_p0=80 , .o_words=10 , .o_bytes=40 , .ib_out=-1 , .in_buffer_idx=1 , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=0 , .is_flatten=0 , .is_softmax=1 , .x_pad=0 , .b_val_shift=0 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=3 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=3 , .csh=1 , .csh_shift=0 , .pkh=1 , .psh=1 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .pkw=1 , .psw=1 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0.875 , .header= 44121212804923392u, .debug_nhwc_words=10 }
{.n=1 , .l=2 , .kw=1 , .coe=96 , .h=14 , .w=14 , .ci=256 , .co=1024, .w_kw2=14 , .t=11 , .p=1 , .cm=512, .cm_p0=256, .on=1 , .oh=14 , .ow=14 , .oc=1024, .ch=14 , .ph=14 , .cw=14 , .pw=14 , .pkh=1 , .psh=1 , .pkw=1 , .psw=1 , .xp_words=196 , .b_offset=0 , .w_bpt=12288, .w_bpt_p0=12288, .x_bpt=25088 , .x_bpt_p0=25088 , .o_words=200704 , .o_bytes=100352 , .ib_out=1 , .in_buffer_idx=-1 , .out_buffer_idx=0 , .add_out_buffer_idx=0 , .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 2303582550611202152u, .debug_nhwc_words=200704 },
{.n=1 , .l=2 , .kw=1 , .coe=96 , .h=14 , .w=14 , .ci=1024, .co=256 , .w_kw2=14 , .t=3 , .p=2 , .cm=512, .cm_p0=512, .on=1 , .oh=14 , .ow=14 , .oc=256 , .ch=14 , .ph=14 , .cw=14 , .pw=14 , .pkh=1 , .psh=1 , .pkw=1 , .psw=1 , .xp_words=196 , .b_offset=1056 , .w_bpt=24576, .w_bpt_p0=24576, .x_bpt=50176 , .x_bpt_p0=50176 , .o_words=78848 , .o_bytes=39424 , .ib_out=2 , .in_buffer_idx=0 , .out_buffer_idx=1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=0 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 2305834350559105128u, .debug_nhwc_words=50176 },
{.n=1 , .l=2 , .kw=3 , .coe=32 , .h=14 , .w=14 , .ci=256 , .co=256 , .w_kw2=13 , .t=8 , .p=2 , .cm=170, .cm_p0=86 , .on=1 , .oh=14 , .ow=14 , .oc=256 , .ch=14 , .ph=14 , .cw=14 , .pw=14 , .pkh=1 , .psh=1 , .pkw=1 , .psw=1 , .xp_words=308 , .b_offset=1344 , .w_bpt=24480, .w_bpt_p0=12384, .x_bpt=26180 , .x_bpt_p0=13244 , .o_words=50176 , .o_bytes=25088 , .ib_out=3 , .in_buffer_idx=1 , .out_buffer_idx=0 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=4 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=0 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 2294592851648450665u, .debug_nhwc_words=50176 },
{.n=1 , .l=2 , .kw=1 , .coe=96 , .h=14 , .w=14 , .ci=256 , .co=1024, .w_kw2=14 , .t=11 , .p=1 , .cm=512, .cm_p0=256, .on=1 , .oh=14 , .ow=14 , .oc=1024, .ch=14 , .ph=14 , .cw=14 , .pw=14 , .pkh=1 , .psh=1 , .pkw=1 , .psw=1 , .xp_words=196 , .b_offset=1600 , .w_bpt=12288, .w_bpt_p0=12288, .x_bpt=25088 , .x_bpt_p0=25088 , .o_words=200704 , .o_bytes=100352 , .ib_out=4 , .in_buffer_idx=0 , .out_buffer_idx=1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=0 , .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=1 , .csh_shift=0 , .psh_shift=0 , .csw=1 , .csw_shift=0 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 2303582550611202152u, .debug_nhwc_words=200704 },
{.n=1 , .l=2 , .kw=1 , .coe=96 , .h=14 , .w=14 , .ci=1024, .co=2048, .w_kw2=14 , .t=22 , .p=2 , .cm=512, .cm_p0=512, .on=1 , .oh=7 , .ow=7 , .oc=2048, .ch=7 , .ph=7 , .cw=7 , .pw=7 , .pkh=1 , .psh=1 , .pkw=1 , .psw=1 , .xp_words=196 , .b_offset=2656 , .w_bpt=24576, .w_bpt_p0=24576, .x_bpt=50176 , .x_bpt_p0=50176 , .o_words=100352 , .o_bytes=401408 , .ib_out=-1 , .in_buffer_idx=1 , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1 , .is_flatten=0 , .is_softmax=0 , .x_pad=0 , .b_val_shift=9 , .b_bias_shift=0 , .ca_nzero=1 , .ca_shift=12 , .ca_pl_scale=0 , .aa_nzero=0 , .aa_shift=0 , .aa_pl_scale=0 , .pa_nzero=0 , .pa_shift=0 , .pa_pl_scale=0 , .softmax_frac=0 , .csh=2 , .csh_shift=0 , .psh_shift=0 , .csw=2 , .csw_shift=0 , .psw_shift=0 , .pool=POOL_NONE , .softmax_max_f=0 , .header= 2305834350559105128u, .debug_nhwc_words=100352 }
};

#define X_BITS_L2 2
#define W_BITS_L2 2
#define KH_MAX 9
#define PE_ROWS 8
#define PE_COLS 24
#define PE_ROWS 7
#define PE_COLS 96

#define N_OUT_BUF 2
#define N_ADD_BUF 2
#define WB_BYTES 13072
#define W_BYTES 12876
#define X_BYTES 672
#define O_WORDS 10
#define O_WORDS_MAX 5600
#define O_BYTES_MAX 2800
#define X_BYTES_ALL 6192
#define NHWC_WORDS 6272
#define N_ADD_BUF 1
#define WB_BYTES 1803584
#define W_BYTES 1794048
#define X_BYTES 25088
#define O_WORDS 100352
#define O_WORDS_MAX 200704
#define O_BYTES_MAX 401408
#define X_BYTES_ALL 290304
#define NHWC_WORDS 401408
#define Y_TYPE int32_t
#define B_TYPE int16_t
#define O_TYPE float
#define B_WORDS 98
#define O_TYPE int32_t
#define B_WORDS 4768
#define AXI_WIDTH 128
#define CONFIG_BASEADDR 0xB0000000
#define DATA_DIR "../vectors"
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12 changes: 6 additions & 6 deletions run/work/config_hw.svh
Original file line number Diff line number Diff line change
Expand Up @@ -3,23 +3,23 @@

`define OR_NEGEDGE(RSTN) or negedge RSTN

`define ROWS 8 // PE rows, constrained by resources
`define COLS 24 // PE cols, constrained by resources
`define ROWS 7 // PE rows, constrained by resources
`define COLS 96 // PE cols, constrained by resources
`define X_BITS 4 // Bits per word in input
`define K_BITS 4 // Bits per word in input
`define Y_BITS 32 // Bits per word in output of conv
`define Y_BITS 20 // Bits per word in output of conv
`define Y_OUT_BITS 32 // Padded bits per word in output of conv

`define KH_MAX 9 // max of kernel height, across layers
`define KW_MAX 9 // max of kernel width, across layers
`define XH_MAX 512 // max of input image height, across layers
`define XW_MAX 512 // max of input image width, across layers
`define XN_MAX 64 // max of input batch size, across layers
`define CI_MAX 2048 // max of input channels, across layers
`define CI_MAX 512 // max of input channels, across layers
`define MAX_N_BUNDLES 64 // max number of bundles in a network
`define CONFIG_BEATS 0 // constant, for now
`define RAM_WEIGHTS_DEPTH 20 // CONFIG_BEATS + max(KW * CI), across layers
`define RAM_EDGES_DEPTH 288 // max (KW * CI * XW), across layers when KW != 1
`define RAM_WEIGHTS_DEPTH 512 // CONFIG_BEATS + max(KW * CI), across layers
`define RAM_EDGES_DEPTH 3584 // max (KW * CI * XW), across layers when KW != 1
`define W_BPT 32 // Width of output integer denoting bytes per transfer

`define DELAY_MUL 3 // constant, for now
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10 changes: 5 additions & 5 deletions run/work/config_hw.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -2,14 +2,14 @@
# Written from Hardware.export()

set FREQ 250
set ROWS 8
set COLS 24
set ROWS 7
set COLS 96
set X_BITS 4
set K_BITS 4
set Y_BITS 32
set Y_BITS 20
set DELAY_W_RAM 2
set RAM_WEIGHTS_DEPTH 20
set RAM_EDGES_DEPTH 288
set RAM_WEIGHTS_DEPTH 512
set RAM_EDGES_DEPTH 3584
set KH_MAX 9
set AXI_WIDTH 128
set CONFIG_BASEADDR 0xB0000000
4 changes: 2 additions & 2 deletions run/work/config_tb.svh
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@

`define VALID_PROB 100
`define READY_PROB 10
`define VALID_PROB 1000
`define READY_PROB 1000
`define CLK_PERIOD 4.0
`define INPUT_DELAY_NS 0.8ns
`define OUTPUT_DELAY_NS 0.8ns
16 changes: 8 additions & 8 deletions run/work/hardware.json
Original file line number Diff line number Diff line change
@@ -1,27 +1,27 @@
{
"processing_elements": [
8,
24
7,
96
],
"frequency_mhz": 250,
"bits_input": 4,
"bits_weights": 4,
"bits_sum": 32,
"bits_sum": 20,
"bits_bias": 16,
"max_batch_size": 64,
"max_channels_in": 2048,
"max_channels_in": 512,
"max_kernel_size": 9,
"max_image_size": 512,
"max_n_bundles": 64,
"ram_weights_depth": 20,
"ram_edges_depth": 288,
"ram_weights_depth": 512,
"ram_edges_depth": 3584,
"axi_width": 128,
"header_width": 64,
"config_baseaddr": "B0000000",
"axi_max_burst_len": 16,
"target_cpu_int_bits": 32,
"async_resetn": true,
"valid_prob": 0.1,
"ready_prob": 0.01,
"valid_prob": 1,
"ready_prob": 1,
"data_dir": "vectors"
}
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