Make config & mem baseaddr a function argument, to support virtual mem

deepsocflow/c/deepsocflow_xilinx.h

@@ -39,11 +39,11 @@ static inline void hardware_cleanup(){
   cleanup_platform();
 }
 
-static inline void model_run_timed(int n){
+static inline void model_run_timed(void *mp, void *p_config, int n){
   XTime time_start, time_end;
   XTime_GetTime(&time_start);
   for (int i=0; i<n; i++)
-    model_run();
+    model_run(mp, p_config);
   XTime_GetTime(&time_end);
   printf("Done inference! time taken: %.5f ms \n", 1000.0*(float)(time_end-time_start)/COUNTS_PER_SECOND/n);
 }

deepsocflow/c/xilinx_example.c

@@ -6,11 +6,18 @@ int main()
 {
     hardware_setup();
 
-    xil_printf("Welcome to DeepSoCFlow!\n Store wbx at: %p; y:%p; buffers {0:%p,1:%p};\n", &mem.w, &mem.y, &mem.out_buffers[0], &mem.out_buffers[1]);
+    // For baremetal, give physical address
+    Memory_st *p_mem = (Memory_st *)MEM_BASEADDR;
+    void *p_config = (void *)CONFIG_BASEADDR;
+    // For linux, give virtual address
+    // Memory_st *p_mem = (Memory_st *)mmap(NULL, sizeof(Memory_st), PROT_READ | PROT_WRITE, MAP_SHARED, dh, MEM_BASEADDR);
+    // void *p_config = mmap(NULL, 4*16+N_BUNDLES*32, PROT_READ | PROT_WRITE, MAP_SHARED, dh, CONFIG_BASEADDR);
 
-    model_setup();
-    model_run_timed(20);    // run model and measure time
-    print_output();
+    xil_printf("Welcome to DeepSoCFlow!\n Store wbx at: %p; y:%p; buffers {0:%p,1:%p};\n", &p_mem->w, &mp->y, &p_mem->out_buffers[0], &p_mem->out_buffers[1]);
+
+    model_setup(p_mem, p_config);
+    model_run_timed(p_mem, p_config, 20);    // run model and measure time
+    print_output(p_mem);
 
     hardware_cleanup();
     return 0;

deepsocflow/py/dataflow.py

@@ -157,7 +157,7 @@ def reorder_b_q2e_conv(b, hw, r):
 
 
 def reorder_w_q2e_conv(w, hw, r):
-
+    # (KH, KW, Ci, CO)
     w = np.pad(w, ((0,0),(0,0),(0,0),(0,r.CO_PAD-r.CO)))        # (KH, KW, CI, CO_PAD)
     w = w.reshape(r.KH, r.KW, r.CI, r.IT, r.CO_PRL)             # (KH, KW, CI, IT, CO_PRL)
     w = np.flip(w, axis=4)                                      # cuz we shift outputs towards right in PE array and read from high col

deepsocflow/py/xmodel.py

@@ -318,8 +318,8 @@ def export_inference(model, hw):
                     np.savetxt(f"{hw.DATA_DIR}/{b.ib}_{ip}_{it}_w.txt", wp, fmt='%d')
                     np.savetxt(f"{hw.DATA_DIR}/{b.ib}_{ip}_{it}_y_exp.txt", b.ye_exp_p[ip][it].flatten(), fmt='%d')
 
-        y_exp = BUNDLES[-1].o_int.flatten()
-        np.savetxt(f"{hw.DATA_DIR}/y_exp.txt", y_exp, fmt= '%f' if BUNDLES[-1].softmax else '%d')
+        y_exp = (b.out.ftensor.numpy() if b.softmax else b.o_int).flatten() 
+        np.savetxt(f"{hw.DATA_DIR}/y_exp.txt", y_exp, fmt= '%f' if b.softmax else '%d')
         for i in range(len(y_exp)):
             if (i < 20 or len(y_exp)-i < 20):
                 print(f"y_exp {i}: {y_exp[i]}")

deepsocflow/test/sv/axi_sys_tb.sv

@@ -55,17 +55,19 @@ module axi_sys_tb;
   export "DPI-C" function set_config;
   import "DPI-C" context function byte get_byte_a32 (int unsigned addr);
   import "DPI-C" context function void set_byte_a32 (int unsigned addr, byte data);
-  import "DPI-C" context function void model_setup();
-  import "DPI-C" context function bit  model_run();
+  import "DPI-C" context function chandle get_mp ();
+  import "DPI-C" context function void print_output (chandle mpv);
+  import "DPI-C" context function void model_setup(chandle mpv, chandle p_config);
+  import "DPI-C" context function bit  model_run(chandle mpv, chandle p_config);
 
 
-  function automatic int get_config(input int offset);
+  function automatic int get_config(chandle config_base, input int offset);
     if (offset < 16)  return dut.OC_TOP.CONTROLLER.cfg        [offset   ];
     else              return dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset-16];
   endfunction
 
 
-  function automatic set_config(input int offset, input int data);
+  function automatic set_config(chandle config_base, input int offset, input int data);
     if (offset < 16) dut.OC_TOP.CONTROLLER.cfg        [offset   ] <= data;
     else             dut.OC_TOP.CONTROLLER.sdp_ram.RAM[offset-16] <= data;
   endfunction
@@ -93,15 +95,19 @@ module axi_sys_tb;
     // $finish;
   end
 
+  chandle mpv, cp;
   initial begin
     rstn = 0;
     repeat(2) @(posedge clk) #10ps;
     rstn = 1;
+    mpv = get_mp();
 
-    model_setup();
+    model_setup(mpv, cp);
     repeat(2) @(posedge clk) #10ps;
 
-    while (model_run()) @(posedge clk) #10ps;
+    while (model_run(mpv, cp)) @(posedge clk) #10ps;
+
+    print_output(mpv);
     $finish;
   end
 

run/param_test.py

@@ -16,15 +16,13 @@
 
 from deepsocflow import *
 
-
-(SIM, SIM_PATH) = ('xsim', "/opt/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
-np.random.seed(42)
+(SIM, SIM_PATH) = ('xsim', "F:/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
 
 '''
 Dataset
 '''
 
-NB_EPOCH = 2
+NB_EPOCH = 0
 BATCH_SIZE = 64
 VALIDATION_SPLIT = 0.1
 NB_CLASSES = 10
@@ -193,8 +191,8 @@ def product_dict(**kwargs):
                                         axi_width            = [ 128      ],
                                         config_baseaddr      = ["B0000000"],
                                         target_cpu_int_bits  = [ 32       ],
-                                        valid_prob           = [ 1       ],
-                                        ready_prob           = [ 1       ],
+                                        valid_prob           = [ 0.1       ],
+                                        ready_prob           = [ 0.01       ],
                                         data_dir             = ['vectors'],
                                     )))
 def test_dnn_engine(PARAMS):

run/work/config_tb.svh

@@ -1,6 +1,6 @@
 
-`define VALID_PROB 1000 
-`define READY_PROB 1000 
+`define VALID_PROB 100 
+`define READY_PROB 10 
 `define CLK_PERIOD 4.0 
 `define INPUT_DELAY_NS  0.8ns
 `define OUTPUT_DELAY_NS 0.8ns

run/work/hardware.json

@@ -21,7 +21,7 @@
     "axi_max_burst_len": 16,
     "target_cpu_int_bits": 32,
     "async_resetn": true,
-    "valid_prob": 1,
-    "ready_prob": 1,
+    "valid_prob": 0.1,
+    "ready_prob": 0.01,
     "data_dir": "vectors"
 }

run/work/sources.txt

@@ -1,29 +1,29 @@
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/cgra4ml_axi2ram_tb.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/axi_sys_tb.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/axi_addr.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/skidbuffer.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/zipcpu_axi2ram.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axi_cgra4ml.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/dnn_engine.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_register.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_pipeline_register.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/xilinx_spwf.v
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_out_shift.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/n_delay.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ram.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/proc_engine.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/cyclic_bram.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/counter.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_weight_rotator.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_pixels.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/dma_controller.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_wr.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axi_dma_wr.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axi_dma_rd.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_rd.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/xilinx_sdp.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_adapter.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_adapter_any.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_ram.sv
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/run/work/config_hw.svh
-/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/run/work/config_tb.svh
+/mnt/d/dnn-engine/deepsocflow/test/sv/axi_sys_tb.sv
+/mnt/d/dnn-engine/deepsocflow/test/sv/cgra4ml_axi2ram_tb.sv
+/mnt/d/dnn-engine/deepsocflow/test/sv/ext/axi_addr.v
+/mnt/d/dnn-engine/deepsocflow/test/sv/ext/skidbuffer.v
+/mnt/d/dnn-engine/deepsocflow/test/sv/ext/zipcpu_axi2ram.v
+/mnt/d/dnn-engine/deepsocflow/rtl/axi_cgra4ml.v
+/mnt/d/dnn-engine/deepsocflow/rtl/dnn_engine.v
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_pipeline_register.v
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_register.v
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/xilinx_spwf.v
+/mnt/d/dnn-engine/deepsocflow/rtl/axis_out_shift.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/axis_pixels.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/axis_weight_rotator.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/counter.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/cyclic_bram.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/dma_controller.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/n_delay.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/proc_engine.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ram.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_ram.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_rd.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axilite_wr.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_adapter.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axis_adapter_any.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axi_dma_rd.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/alex_axi_dma_wr.sv
+/mnt/d/dnn-engine/deepsocflow/rtl/ext/xilinx_sdp.sv
+/mnt/d/dnn-engine/run/work/config_hw.svh
+/mnt/d/dnn-engine/run/work/config_tb.svh

run/work/vivado_flow.tcl

@@ -1,8 +1,8 @@
 
 set PROJECT_NAME dsf_zcu104
-set RTL_DIR      /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl
+set RTL_DIR      /mnt/d/dnn-engine/deepsocflow/rtl
 set CONFIG_DIR   .
 
 source config_hw.tcl
-source /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/tcl/fpga/zcu104.tcl
-source /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/tcl/fpga/vivado.tcl
+source /mnt/d/dnn-engine/deepsocflow/tcl/fpga/zcu104.tcl
+source /mnt/d/dnn-engine/deepsocflow/tcl/fpga/vivado.tcl