Tested multiple runs

KastnerRG · Jul 23, 2024 · 6523d43 · 6523d43
1 parent c33558c
commit 6523d43
Show file tree

Hide file tree

Showing 4 changed files with 17 additions and 16 deletions.
diff --git a/deepsocflow/c/deepsocflow_xilinx.h b/deepsocflow/c/deepsocflow_xilinx.h
@@ -39,11 +39,12 @@ static inline void hardware_cleanup(){
   cleanup_platform();
 }
 
-static inline void model_run_timed(){
+static inline void model_run_timed(int n){
   XTime time_start, time_end;
   XTime_GetTime(&time_start);
-  model_run();
+  for (int i=0; i<n; i++)
+    model_run();
   XTime_GetTime(&time_end);
-  printf("Done inference! time taken: %.5f ms \n", 1000.0*(float)(time_end-time_start)/COUNTS_PER_SECOND);
+  printf("Done inference! time taken: %.5f ms \n", 1000.0*(float)(time_end-time_start)/COUNTS_PER_SECOND/n);
 }
 
diff --git a/deepsocflow/c/xilinx_example.c b/deepsocflow/c/xilinx_example.c
@@ -9,7 +9,7 @@ int main()
     xil_printf("Welcome to DeepSoCFlow!\n Store wbx at: %p; y:%p; buffers {0:%p,1:%p};\n", &mem.w, &mem.y, &mem.out_buffers[0], &mem.out_buffers[1]);
 
     model_setup();
-    model_run_timed();    // run model and measure time
+    model_run_timed(20);    // run model and measure time
     print_output();
 
     hardware_cleanup();

diff --git a/deepsocflow/py/xmodel.py b/deepsocflow/py/xmodel.py
@@ -351,13 +351,13 @@ def verify_inference(model, hw, SIM, SIM_PATH):
         for ip in range(b.r.CP):
             for it in range(b.r.IT):
                 y_raw_exp = b.ye_exp_p[ip][it]
-                y_raw_sim = np.loadtxt(f"{hw.DATA_DIR}/{b.ib}_{ip}_{it}_y_raw_sim.txt", np.int32).reshape(y_raw_exp.shape)
+                y_raw_sim = np.loadtxt(f"{hw.DATA_DIR}/{b.ib}_{ip}_{it}_y_raw_sim.txt", np.int32)[:y_raw_exp.size].reshape(y_raw_exp.shape)
                 error = np.sum(np.abs(y_raw_exp-y_raw_sim))
                 assert error == 0, f"Error={error}, for y_raw_sim at {b.ib=}_{ip=}_{it=}"
 
         ''' Verify sum output '''
         y_sum_exp = b.oe_sum_exp
-        y_sum_sim = np.loadtxt(f"{hw.DATA_DIR}/{b.ib}_y_sum_sim.txt", np.int32).reshape(y_sum_exp.shape)
+        y_sum_sim = np.loadtxt(f"{hw.DATA_DIR}/{b.ib}_y_sum_sim.txt", np.int32)[:y_sum_exp.size].reshape(y_sum_exp.shape)
         error = np.sum(np.abs(y_sum_exp-y_sum_sim))
         assert error == 0, f"Error={error}, for y_sum_sim at {b.ib=}"
 

diff --git a/deepsocflow/rtl/dma_controller.sv b/deepsocflow/rtl/dma_controller.sv
@@ -249,19 +249,19 @@ module dma_controller #(
 
   always_ff @(posedge clk) // All cfg written in this always block
     if (!rstn) begin 
-      cfg[A_START] <= 0; 
-      cfg[A_DONE_READ+0] <= 32'd1;
-      cfg[A_DONE_READ+1] <= 32'd1;
+      cfg[A_START       ] <= 0; 
+      cfg[A_DONE_READ +0] <= 32'd1;
+      cfg[A_DONE_READ +1] <= 32'd1;
       cfg[A_DONE_WRITE+0] <= 32'd0;
       cfg[A_DONE_WRITE+1] <= 32'd0;
-      cfg[A_OCM_BASE+0] <= 32'd0;
-      cfg[A_OCM_BASE+1] <= 32'd0;
+      cfg[A_OCM_BASE  +0] <= 32'd0;
+      cfg[A_OCM_BASE  +1] <= 32'd0;
       cfg[A_WEIGHTS_BASE] <= 32'd0;
-      cfg[A_BUNDLE_DONE] <= 32'd1;
-      cfg[A_N_BUNDLES_1] <= 32'd0;
-      cfg[A_W_DONE] <= 32'd0;
-      cfg[A_X_DONE] <= 32'd0;
-      cfg[A_O_DONE] <= 32'd0;
+      cfg[A_BUNDLE_DONE ] <= 32'd1;
+      cfg[A_N_BUNDLES_1 ] <= 32'd0;
+      cfg[A_W_DONE      ] <= 32'd0;
+      cfg[A_X_DONE      ] <= 32'd0;
+      cfg[A_O_DONE      ] <= 32'd0;
 
       ocm_idx     <= 1; // before first transfer idx = 1, so first idx = 0
       m_od_addr   <= 0;