Fix vivado flow

.gitignore

@@ -22,6 +22,7 @@ deepsocflow/test/py/*
 
 run/work/vectors/*
 run/work/build/*
+run/work/dsf*
 
 
 # Distribution / packaging

deepsocflow/fpga/scripts/pynq_z2.tcl

@@ -1,8 +1,7 @@
 set BOARD pynq_z2
-set FREQ  99
 
 create_project ${PROJECT_NAME} ${PROJECT_NAME} -part xc7z020clg400-1 -force
-# set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
+set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project]
 
 create_bd_design "design_1"
 create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0

deepsocflow/fpga/scripts/vivado.tcl

@@ -1,14 +1,3 @@
-set PROJECT_NAME sys_accl
-set RTL_DIR ../../rtl
-set SCRIPTS_DIR ../scripts
-source $SCRIPTS_DIR/vivado_config.tcl
-
-#Board specific
-source $SCRIPTS_DIR/pynq_z2.tcl
-# source $SCRIPTS_DIR/zcu102.tcl
-# source $SCRIPTS_DIR/zcu104.tcl
-
-
 # CREATE IPs
 set IP_NAME "ram_weights"
 set WIDTH [expr "$COLS * $K_BITS"]
@@ -67,7 +56,7 @@ apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config "Clk_master {Auto} Clk
 
 
 # Engine
-add_files -norecurse -scan_for_includes [glob $RTL_DIR/*]
+add_files  [glob $CONFIG_DIR/*.svh] [glob $RTL_DIR/*] [glob $RTL_DIR/ext/*]
 set_property top dnn_engine [current_fileset]
 create_bd_cell -type module -reference dnn_engine dnn_engine_0
 
@@ -98,12 +87,12 @@ write_hw_platform -fixed -include_bit -force -file design_1_wrapper.xsa
 
 # Reports
 open_run impl_1
-if {![file exists ../reports]} {exec mkdir ../reports}
-report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 100 -input_pins -routable_nets -name timing_1 -file ../reports/${PROJECT_NAME}_${BOARD}_${FREQ}_timing_report.txt
-report_utilization -file ../reports/${PROJECT_NAME}_${BOARD}_${FREQ}_utilization_report.txt -name utilization_1
-report_power -file ../reports/${PROJECT_NAME}_${BOARD}_${FREQ}_power_1.txt -name {power_1}
-report_drc -name drc_1 -file ../reports/${PROJECT_NAME}_${BOARD}_${FREQ}_drc_1.txt -ruledecks {default opt_checks placer_checks router_checks bitstream_checks incr_eco_checks eco_checks abs_checks}
-
-exec mkdir -p ../output
-exec cp "$PROJECT_NAME/$PROJECT_NAME.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh" ../output/
-exec cp "$PROJECT_NAME/$PROJECT_NAME.runs/impl_1/design_1_wrapper.bit" ../output/design_1.bit
+if {![file exists reports]} {exec mkdir reports}
+report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 100 -input_pins -routable_nets -name timing_1 -file reports/${PROJECT_NAME}_${BOARD}_${FREQ}_timing_report.txt
+report_utilization -file $PROJECT_NAME/reports/${PROJECT_NAME}_${BOARD}_${FREQ}_utilization_report.txt -name utilization_1
+report_power -file reports/${PROJECT_NAME}_${BOARD}_${FREQ}_power_1.txt -name {power_1}
+report_drc -name drc_1 -file reports/${PROJECT_NAME}_${BOARD}_${FREQ}_drc_1.txt -ruledecks {default opt_checks placer_checks router_checks bitstream_checks incr_eco_checks eco_checks abs_checks}
+
+exec mkdir -p $PROJECT_NAME/output
+exec cp "$PROJECT_NAME/$PROJECT_NAME.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh" $PROJECT_NAME/output/
+exec cp "$PROJECT_NAME/$PROJECT_NAME.runs/impl_1/design_1_wrapper.bit" $PROJECT_NAME/output/design_1.bit

deepsocflow/fpga/scripts/zcu104.tcl

@@ -1,11 +1,10 @@
 set BOARD zcu104
-set FREQ  249
 
 create_project ${PROJECT_NAME} ${PROJECT_NAME} -part xczu7ev-ffvc1156-2-e -force
 set_property board_part xilinx.com:zcu104:part0:1.1 [current_project]
 
 create_bd_design "design_1"
-create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0
+create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.4 zynq_ultra_ps_e_0
 apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" }  [get_bd_cells zynq_ultra_ps_e_0]
 set_property -dict [list CONFIG.PSU__USE__M_AXI_HPM0_LPD {0} CONFIG.PSU__USE__M_AXI_GP1 {1} CONFIG.PSU__USE__S_AXI_GP0 {1} CONFIG.PSU__USE__M_AXI_GP2 {1} CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ $FREQ CONFIG.PSU__USE__M_AXI_GP0 {0}] [get_bd_cells zynq_ultra_ps_e_0]
 

deepsocflow/py/hardware.py

@@ -94,7 +94,7 @@ def __init__(
         self.BITS_XN_MAX           = clog2(self.XN_MAX)
         self.BITS_RAM_WEIGHTS_ADDR = clog2(self.RAM_WEIGHTS_DEPTH)
 
-        self.MODULE_DIR = os.path.dirname(deepsocflow.__file__)
+        self.MODULE_DIR = os.path.normpath(os.path.dirname(deepsocflow.__file__)).replace('\\', '/')
         self.TB_MODULE = "dnn_engine_tb"
         self.WAVEFORM = "dnn_engine_tb_behav.wcfg"
         self.SOURCES = glob.glob(f'{self.MODULE_DIR}/test/sv/*.sv') + glob.glob(f"{self.MODULE_DIR}/rtl/**/*.v", recursive=True) + glob.glob(f"{self.MODULE_DIR}/rtl/**/*.sv", recursive=True) + glob.glob(f"{os.getcwd()}/*.svh")
@@ -164,14 +164,15 @@ def export(self):
         with open('config_hw.tcl', 'w') as f:
             f.write(f'''
 # Written from Hardware.export()
-                    
-set RAM_WEIGHTS_DEPTH  {self.RAM_WEIGHTS_DEPTH}
+
+set FREQ               {self.FREQ}
 set ROWS               {self.ROWS}
 set COLS               {self.COLS}
 set X_BITS             {self.X_BITS}
 set K_BITS             {self.K_BITS}
 set Y_BITS             {self.Y_BITS}
 set DELAY_W_RAM        2
+set RAM_WEIGHTS_DEPTH  {self.RAM_WEIGHTS_DEPTH}
 set RAM_EDGES_DEPTH    {self.RAM_EDGES_DEPTH}
 set KH_MAX             {self.KH_MAX}
 set S_WEIGHTS_WIDTH_LF {self.IN_BITS}
@@ -211,4 +212,29 @@ def simulate(self, SIM='verilator', SIM_PATH=''):
         if SIM == 'icarus':
             subprocess.run(["vvp", "build/a.out"])
         if SIM == 'verilator':
-            subprocess.run([f"./V{self.TB_MODULE}"], cwd="build")
+            subprocess.run([f"./V{self.TB_MODULE}"], cwd="build")
+
+
+    def export_vivado_tcl(self, board='zcu104', rtl_dir_abspath=None, scripts_dir_abspath=None, board_tcl_abspath=None):
+
+        if rtl_dir_abspath is None:
+            rtl_dir_abspath = self.MODULE_DIR + '/rtl'
+        if scripts_dir_abspath is None:
+            scripts_dir_abspath = self.MODULE_DIR + '/fpga/scripts'
+        if board_tcl_abspath is None:
+            board_tcl_abspath = f'{scripts_dir_abspath}/{board}.tcl'
+
+        assert os.path.exists(board_tcl_abspath), f"Board script {board_tcl_abspath} does not exist."
+        assert os.path.exists('./config_hw.tcl'), f"./config_hw.tcl does not exist."
+
+        with open('vivado_flow.tcl', 'w') as f:
+            f.write(f'''
+set PROJECT_NAME dsf_{board}
+set RTL_DIR      {rtl_dir_abspath}
+set CONFIG_DIR   .
+
+source config_hw.tcl
+source {board_tcl_abspath}
+source {scripts_dir_abspath}/vivado.tcl
+''')
+        exit()

run/param_test.py

@@ -45,6 +45,7 @@
 hw.export_json()
 hw = Hardware.from_json('hardware.json')
 hw.export() # Generates: config_hw.svh, config_hw.tcl
+hw.export_vivado_tcl(board='zcu104')
 
 
 def test_dnn_engine():

run/work/config_hw.tcl

@@ -1,13 +1,14 @@
 
 # Written from Hardware.export()
-                    
-set RAM_WEIGHTS_DEPTH  20
+
+set FREQ               250
 set ROWS               8
-set COLS               24
+set COLS               96
 set X_BITS             4
 set K_BITS             4
-set Y_BITS             24
+set Y_BITS             16
 set DELAY_W_RAM        2
+set RAM_WEIGHTS_DEPTH  20
 set RAM_EDGES_DEPTH    288
 set KH_MAX             13
 set S_WEIGHTS_WIDTH_LF 64

run/work/vivado_flow.tcl

@@ -0,0 +1,8 @@
+
+set PROJECT_NAME dsf_zcu104
+set RTL_DIR      D:/dnn-engine/deepsocflow/rtl
+set CONFIG_DIR   .
+
+source config_hw.tcl
+source D:/dnn-engine/deepsocflow/fpga/scripts/zcu104.tcl
+source D:/dnn-engine/deepsocflow/fpga/scripts/vivado.tcl