Fix verilog errors, python warnings

KastnerRG · Nov 29, 2023 · a088f92 · a088f92
1 parent 91066c8
commit a088f92
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Showing 4 changed files with 6 additions and 7 deletions.
diff --git a/deepsocflow/py/model.py b/deepsocflow/py/model.py
@@ -239,7 +239,7 @@ def export_inference(self, x, hw):
                 x_config = format(x_config, f'#0{hw.IN_BITS}b')
                 x_config_words = [int(x_config[i:i+hw.X_BITS], 2) for i in range(0, len(x_config), hw.X_BITS)]
                 x_config_words.reverse()
-                x_config_words = np.array(x_config_words, dtype=np.int8)
+                x_config_words = np.array(x_config_words, dtype=np.uint8)
 
                 xp = b.xe[ip].flatten()
                 xp = np.concatenate([x_config_words, xp], axis=0)
@@ -253,7 +253,7 @@ def export_inference(self, x, hw):
                     w_config = format(w_config, f'#0{hw.IN_BITS}b')
                     w_config_words = [int(w_config[i:i+hw.K_BITS], 2) for i in range(0, len(w_config), hw.K_BITS)]
                     w_config_words.reverse()
-                    w_config_words = np.array(w_config_words,dtype=np.int8)
+                    w_config_words = np.array(w_config_words, dtype=np.uint8)
 
                     wp = b.we[ip][it].flatten()            
                     wp = np.concatenate([w_config_words, wp], axis=0)

diff --git a/deepsocflow/rtl/dnn_engine.v b/deepsocflow/rtl/dnn_engine.v
@@ -153,14 +153,14 @@ module dnn_engine #(
     .s_axis_tdata  (m_data_padded),
     .s_axis_tlast  (m_last       ),
     .s_axis_tkeep  ({(Y_BITS_PADDED*ROWS/8){1'b1}}),
-    .s_axis_tid    ('0         ),
-    .s_axis_tdest  ('0         ),
-    .s_axis_tuser  ('0         ),
     .m_axis_tready (m_axis_tready),
     .m_axis_tvalid (m_axis_tvalid),
     .m_axis_tdata  (m_axis_tdata ),
     .m_axis_tlast  (m_axis_tlast ),
     .m_axis_tkeep  (m_axis_tkeep ),
+    .s_axis_tid    (8'b0),
+    .s_axis_tdest  (8'b0),
+    .s_axis_tuser  (1'b0),
     .m_axis_tid    (),
     .m_axis_tdest  (),
     .m_axis_tuser  ()

diff --git a/deepsocflow/rtl/ext/alex_axis_adapter.v → deepsocflow/rtl/ext/alex_axis_adapter.sv b/deepsocflow/rtl/ext/alex_axis_adapter.v → deepsocflow/rtl/ext/alex_axis_adapter.sv
diff --git a/run/work/sources.txt b/run/work/sources.txt
@@ -5,7 +5,6 @@ D:\dnn-engine\deepsocflow\test\sv\dnn_engine_tb.sv
 D:\dnn-engine\deepsocflow\test\sv\ram_raw.sv
 D:\dnn-engine\deepsocflow\test\sv\skid_buffer_tb.sv
 D:\dnn-engine\deepsocflow\rtl\dnn_engine.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter.v
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_pipeline_register.v
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_register.v
 D:\dnn-engine\deepsocflow\rtl\axis_out_shift.sv
@@ -15,9 +14,9 @@ D:\dnn-engine\deepsocflow\rtl\counter.sv
 D:\dnn-engine\deepsocflow\rtl\cyclic_bram.sv
 D:\dnn-engine\deepsocflow\rtl\huffman_2_decoder.sv
 D:\dnn-engine\deepsocflow\rtl\n_delay.sv
-D:\dnn-engine\deepsocflow\rtl\out_ram_switch.sv
 D:\dnn-engine\deepsocflow\rtl\proc_element.sv
 D:\dnn-engine\deepsocflow\rtl\proc_engine.sv
+D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter.sv
 D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter_any.sv
 D:\dnn-engine\run\work\config_hw.svh
 D:\dnn-engine\run\work\config_tb.svh