Verified on FPGA

KastnerRG · Jul 23, 2024 · cc961ce · cc961ce
1 parent ffc8820
commit cc961ce
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Showing 10 changed files with 43 additions and 43 deletions.
diff --git a/deepsocflow/c/deepsocflow_xilinx.h b/deepsocflow/c/deepsocflow_xilinx.h
@@ -25,9 +25,9 @@ static inline void flush_cache(void *addr, uint32_t bytes) {
 }
 
 // RUNTIME.H 
-#define printf xil_printf
+//#define printf xil_printf
 #include "runtime.h"
-#undef printf
+//#undef printf
 
 static inline void hardware_setup(){
   init_platform();

diff --git a/deepsocflow/c/xilinx_example.c b/deepsocflow/c/xilinx_example.c
@@ -1,4 +1,4 @@
-#define XDEBUG
+//#define XDEBUG
 #include "platform.h"
 #include "deepsocflow_xilinx.h"
 

diff --git a/deepsocflow/py/hardware.py b/deepsocflow/py/hardware.py
@@ -223,7 +223,7 @@ def simulate(self, SIM='verilator', SIM_PATH=''):
             assert subprocess.run(cmd).returncode == 0
 
         if SIM == "verilator":
-            cmd = f'{SIM_PATH}verilator --binary -j 0 -O3 --trace --trace-depth 0 --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -DSIM -CFLAGS -I../ {self.MODULE_DIR}/c/sim.c -CFLAGS -g --Mdir ./'
+            cmd = f'{SIM_PATH}verilator --binary -j 0 -O3 --relative-includes --top {self.TB_MODULE} -I../ -F ../sources.txt -CFLAGS -DSIM -CFLAGS -I../ {self.MODULE_DIR}/c/sim.c -CFLAGS -g --Mdir ./'
             print(cmd)
             assert subprocess.run(cmd.split(' '), cwd='build').returncode == 0
 

diff --git a/deepsocflow/rtl/dma_controller.sv b/deepsocflow/rtl/dma_controller.sv
@@ -2,7 +2,7 @@
 
 module dma_controller #(
   parameter
-    SRAM_RD_DATA_WIDTH = 32*9,
+    SRAM_RD_DATA_WIDTH = 32*8,
     SRAM_RD_DEPTH      = 8   , // number of bundles
     COUNTER_WIDTH      = 16  , // T, P, B counters
     AXI_ADDR_WIDTH     = 32  ,

diff --git a/run/param_test.py b/run/param_test.py
@@ -17,7 +17,7 @@
 from deepsocflow import *
 
 
-(SIM, SIM_PATH) = ('xsim', "F:/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
+(SIM, SIM_PATH) = ('xsim', "/opt/Xilinx/Vivado/2022.2/bin/") if os.name=='nt' else ('verilator', '')
 np.random.seed(42)
 
 '''

diff --git a/run/work/config_fw.h b/run/work/config_fw.h
@@ -6,7 +6,7 @@ Bundle_t bundles [N_BUNDLES] = {
    {.n=1  , .l=1  , .kw=5  , .coe=4  , .coe_tl=4  , .r_ll=7  , .h=7  , .w=10 , .ci=8   , .co=8   , .w_kw2=8  , .t=2  , .p=2  , .cm=4  , .cm_p0=4  , .xp_words=120   , .ib_out=4   , .w_bpt=240  , .w_bpt_p0=240  , .x_bpt=240     , .x_bpt_p0=240     , .o_words=960     , .o_bytes=480     , .x_pad=4  , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=0 , .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .b_offset=42   , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .softmax_max_f=0              , .csh=1  , .ch=7  , .csh_shift=0  , .pkh=1  , .psh=1  , .ph=7  , .psh_shift=0  , .csw=1  , .cw=10 , .csw_shift=0  , .pkw=1  , .psw=1  , .pw=10 , .psw_shift=0  , .pool=POOL_NONE , .on=1  , .oh=7  , .ow=10 , .oc=8   , .header=      44121204210794570u, .debug_nhwc_words=560       },
    {.n=1  , .l=1  , .kw=3  , .coe=8  , .coe_tl=8  , .r_ll=7  , .h=7  , .w=10 , .ci=8   , .co=24  , .w_kw2=9  , .t=3  , .p=2  , .cm=6  , .cm_p0=2  , .xp_words=120   , .ib_out=5   , .w_bpt=216  , .w_bpt_p0=72   , .x_bpt=360     , .x_bpt_p0=120     , .o_words=1920    , .o_bytes=960     , .x_pad=4  , .in_buffer_idx=1  , .out_buffer_idx=0  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=0  , .is_softmax=0  , .b_offset=50   , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .softmax_max_f=0              , .csh=1  , .ch=7  , .csh_shift=0  , .pkh=1  , .psh=1  , .ph=7  , .psh_shift=0  , .csw=1  , .cw=10 , .csw_shift=0  , .pkw=1  , .psw=1  , .pw=10 , .psw_shift=0  , .pool=POOL_NONE , .on=1  , .oh=7  , .ow=10 , .oc=24  , .header=      38632443238154313u, .debug_nhwc_words=1680      },
    {.n=1  , .l=1  , .kw=1  , .coe=24 , .coe_tl=0  , .r_ll=7  , .h=7  , .w=10 , .ci=24  , .co=10  , .w_kw2=10 , .t=1  , .p=2  , .cm=20 , .cm_p0=4  , .xp_words=80    , .ib_out=6   , .w_bpt=240  , .w_bpt_p0=48   , .x_bpt=800     , .x_bpt_p0=160     , .o_words=5600    , .o_bytes=2800    , .x_pad=0  , .in_buffer_idx=0  , .out_buffer_idx=1  , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=1  , .is_flatten=1  , .is_softmax=0  , .b_offset=74   , .b_val_shift=9  , .b_bias_shift=0  , .ca_nzero=0  , .ca_shift=12 , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=0  , .softmax_max_f=0              , .csh=1  , .ch=7  , .csh_shift=0  , .pkh=1  , .psh=1  , .ph=7  , .psh_shift=0  , .csw=1  , .cw=10 , .csw_shift=0  , .pkw=1  , .psw=1  , .pw=10 , .psw_shift=0  , .pool=POOL_NONE , .on=1  , .oh=1  , .ow=1  , .oc=700 , .header=      42995312893886536u, .debug_nhwc_words=700       },
-   {.n=1  , .l=1  , .kw=1  , .coe=24 , .coe_tl=0  , .r_ll=1  , .h=1  , .w=1  , .ci=700 , .co=10  , .w_kw2=1  , .t=1  , .p=35 , .cm=20 , .cm_p0=20 , .xp_words=8     , .ib_out=-1  , .w_bpt=240  , .w_bpt_p0=240  , .x_bpt=80      , .x_bpt_p0=80      , .o_words=10      , .o_bytes=40      , .x_pad=0  , .in_buffer_idx=1  , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=0  , .is_flatten=0  , .is_softmax=1  , .b_offset=98   , .b_val_shift=0  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=3  , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=3  , .softmax_max_f=-0.375         , .csh=1  , .ch=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .ph=1  , .psh_shift=0  , .csw=1  , .cw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .pw=1  , .psw_shift=0  , .pool=POOL_NONE , .on=1  , .oh=1  , .ow=1  , .oc=10  , .header=      44121212804923392u, .debug_nhwc_words=10        }
+   {.n=1  , .l=1  , .kw=1  , .coe=24 , .coe_tl=0  , .r_ll=1  , .h=1  , .w=1  , .ci=700 , .co=10  , .w_kw2=1  , .t=1  , .p=35 , .cm=20 , .cm_p0=20 , .xp_words=8     , .ib_out=-1  , .w_bpt=240  , .w_bpt_p0=240  , .x_bpt=80      , .x_bpt_p0=80      , .o_words=10      , .o_bytes=40      , .x_pad=0  , .in_buffer_idx=1  , .out_buffer_idx=-1 , .add_out_buffer_idx=-1, .add_in_buffer_idx=-1, .is_bias=0  , .is_flatten=0  , .is_softmax=1  , .b_offset=98   , .b_val_shift=0  , .b_bias_shift=0  , .ca_nzero=1  , .ca_shift=3  , .ca_pl_scale=0  , .aa_nzero=0  , .aa_shift=0  , .aa_pl_scale=0  , .pa_nzero=0  , .pa_shift=0  , .pa_pl_scale=0  , .softmax_frac=3  , .softmax_max_f=0.875          , .csh=1  , .ch=1  , .csh_shift=0  , .pkh=1  , .psh=1  , .ph=1  , .psh_shift=0  , .csw=1  , .cw=1  , .csw_shift=0  , .pkw=1  , .psw=1  , .pw=1  , .psw_shift=0  , .pool=POOL_NONE , .on=1  , .oh=1  , .ow=1  , .oc=10  , .header=      44121212804923392u, .debug_nhwc_words=10        }
 };
 
 #define X_BITS_L2   2

diff --git a/run/work/config_tb.svh b/run/work/config_tb.svh
@@ -1,6 +1,6 @@
 
-`define VALID_PROB 1000 
-`define READY_PROB 1000 
+`define VALID_PROB 10 
+`define READY_PROB 100 
 `define CLK_PERIOD 4.0 
 `define INPUT_DELAY_NS  0.8ns
 `define OUTPUT_DELAY_NS 0.8ns
diff --git a/run/work/hardware.json b/run/work/hardware.json
@@ -21,7 +21,7 @@
     "axi_max_burst_len": 16,
     "target_cpu_int_bits": 32,
     "async_resetn": true,
-    "valid_prob": 1,
-    "ready_prob": 1,
+    "valid_prob": 0.01,
+    "ready_prob": 0.1,
     "data_dir": "vectors"
 }
diff --git a/run/work/sources.txt b/run/work/sources.txt
@@ -1,29 +1,29 @@
-D:\dnn-engine\deepsocflow\test\sv\axi_sys_tb.sv
-D:\dnn-engine\deepsocflow\test\sv\cgra4ml_axi2ram_tb.sv
-D:\dnn-engine\deepsocflow\test\sv\ext\axi_addr.v
-D:\dnn-engine\deepsocflow\test\sv\ext\skidbuffer.v
-D:\dnn-engine\deepsocflow\test\sv\ext\zipcpu_axi2ram.v
-D:\dnn-engine\deepsocflow\rtl\axi_cgra4ml.v
-D:\dnn-engine\deepsocflow\rtl\dnn_engine.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_pipeline_register.v
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_register.v
-D:\dnn-engine\deepsocflow\rtl\ext\xilinx_spwf.v
-D:\dnn-engine\deepsocflow\rtl\axis_out_shift.sv
-D:\dnn-engine\deepsocflow\rtl\axis_pixels.sv
-D:\dnn-engine\deepsocflow\rtl\axis_weight_rotator.sv
-D:\dnn-engine\deepsocflow\rtl\counter.sv
-D:\dnn-engine\deepsocflow\rtl\cyclic_bram.sv
-D:\dnn-engine\deepsocflow\rtl\dma_controller.sv
-D:\dnn-engine\deepsocflow\rtl\n_delay.sv
-D:\dnn-engine\deepsocflow\rtl\proc_engine.sv
-D:\dnn-engine\deepsocflow\rtl\ram.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_ram.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_rd.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axilite_wr.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axis_adapter_any.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_rd.sv
-D:\dnn-engine\deepsocflow\rtl\ext\alex_axi_dma_wr.sv
-D:\dnn-engine\deepsocflow\rtl\ext\xilinx_sdp.sv
-D:\dnn-engine\run\work\config_hw.svh
-D:\dnn-engine\run\work\config_tb.svh
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/cgra4ml_axi2ram_tb.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/axi_sys_tb.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/axi_addr.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/skidbuffer.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/test/sv/ext/zipcpu_axi2ram.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axi_cgra4ml.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/dnn_engine.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_register.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_pipeline_register.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/xilinx_spwf.v
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_out_shift.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/n_delay.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ram.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/proc_engine.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/cyclic_bram.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/counter.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_weight_rotator.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/axis_pixels.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/dma_controller.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_wr.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axi_dma_wr.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axi_dma_rd.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_rd.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/xilinx_sdp.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_adapter.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axis_adapter_any.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl/ext/alex_axilite_ram.sv
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/run/work/config_hw.svh
+/home/dominus/axi-tb-sys/cgra-remote/cgra4ml/run/work/config_tb.svh
diff --git a/run/work/vivado_flow.tcl b/run/work/vivado_flow.tcl
@@ -1,8 +1,8 @@
 
 set PROJECT_NAME dsf_zcu104
-set RTL_DIR      D:/dnn-engine/deepsocflow/rtl
+set RTL_DIR      /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/rtl
 set CONFIG_DIR   .
 
 source config_hw.tcl
-source D:/dnn-engine/deepsocflow/tcl/fpga/zcu104.tcl
-source D:/dnn-engine/deepsocflow/tcl/fpga/vivado.tcl
+source /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/tcl/fpga/zcu104.tcl
+source /home/dominus/axi-tb-sys/cgra-remote/cgra4ml/deepsocflow/tcl/fpga/vivado.tcl