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RTL Blocks for the Rocket Chip Generator

This repository contains RTL generators for a variety of IO peripheral blocks that are designed to be compatible with the Rocket Chip SoC Generator

This repository is a fork of https://github.com/sifive/sifive-blocks, which it replaces.

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RTL blocks compatible with the Rocket Chip Generator

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  • Scala 99.6%
  • Verilog 0.4%