Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Implements uniform-random distribution of traffic and equal number of physical links in each trunk. Intended for simulation in ModelSim.
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Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Implements uniform-random spatial distribution of traffic and equal number of physical links in each trunk. Intended for simulation in ModelSim.
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GPL-2.0, Unknown licenses found
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KorotkiyEugene/LAG_sv_sim_random_traffic
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Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Implements uniform-random spatial distribution of traffic and equal number of physical links in each trunk. Intended for simulation in ModelSim.
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GPL-2.0, Unknown licenses found
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GPL-2.0
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License.txt
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