Fixed constraint for h2f_user0_clk in sdc file

LampaLab · May 8, 2018 · 255a513 · 255a513
1 parent 5d4c2e3
commit 255a513
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/pow_accel_soc/hardware/constraints.sdc b/pow_accel_soc/hardware/constraints.sdc
@@ -2,7 +2,7 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
 
-create_clock -period 200MHz  [get_ports clock_bridge_0_out_clk_clk]
+create_clock -period 200MHz [get_pins -compatibility_mode u0|hps_0|fpga_interfaces|clocks_resets|h2f_user0_clk]
 
 derive_pll_clocks