π± Sophomore UG @SUSTech
β¨ I'm interested in software engineering and implementing AI/ML into automated testing
π¨βπ» Projects
- SUSTech Projects:
- Other Projects:
π§ Reach me via [email protected]
Contact GitHub support about this userβs behavior. Learn more about reporting abuse.
Report abuseπ± Sophomore UG @SUSTech
β¨ I'm interested in software engineering and implementing AI/ML into automated testing
π¨βπ» Projects
π§ Reach me via [email protected]
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
VHDL 1
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/β¦
Java 1
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Jungle: Chess Game Engine - Implementation of Minimax, Alpha-Beta Pruning, Move Ordering, and Quiescence Search - SUSTech's project of course CS109: Introduction to Programming in Spring 2023 - Scoβ¦
Java 1