Merge branch 'The-OpenROAD-Project:master' into remove_static_vars

CMakeLists.txt

@@ -88,6 +88,7 @@ project(OpenROAD VERSION 1
 )
 
 set(OPENROAD_HOME ${PROJECT_SOURCE_DIR})
+set(OPENROAD_SHARE ${CMAKE_INSTALL_PREFIX}/share/openroad)
 
 # Default c++ standard used unless otherwise specified in target_compile_features.
 set(CMAKE_CXX_STANDARD 17 CACHE STRING "the C++ standard to use for this project")

README.md

@@ -44,7 +44,9 @@ flowchart LR
     subgraph ORFlow
     direction TB
     style ORFlow fill:#ffffff00, stroke-width:0px
-        A[Verilog\n+ libraries\n + constraints] --> FLOW
+        A[Verilog
+        + libraries
+        + constraints] --> FLOW
         style A fill:#74c2b5,stroke:#000000,stroke-width:4px
         subgraph FLOW
         style FLOW fill:#FFFFFF00,stroke-width:4px
@@ -64,7 +66,8 @@ flowchart LR
             style G fill:#ff6666,stroke:#000000,stroke-width:4px
         end
 
-        FLOW --> H[GDSII\n Final Layout]
+        FLOW --> H[GDSII
+        Final Layout]
         %% H --- H1[ ]
         %% style H1 stroke-width:0px, fill: #FFFFFF00
         %% linkStyle 11 stroke-width:0px

src/dbSta/src/dbNetwork.cc

@@ -1778,7 +1778,7 @@ void dbNetwork::makeCell(Library* library, dbMaster* master)
 
   // Fill in liberty to db/LEF master correspondence for libraries not used
   // for corners that are not used for "linking".
-  LibertyLibraryIterator* lib_iter = libertyLibraryIterator();
+  std::unique_ptr<LibertyLibraryIterator> lib_iter{libertyLibraryIterator()};
   while (lib_iter->hasNext()) {
     LibertyLibrary* lib = lib_iter->next();
     LibertyCell* lib_cell = lib->findLibertyCell(cell_name);
@@ -1807,8 +1807,6 @@ void dbNetwork::makeCell(Library* library, dbMaster* master)
     Port* cur_port = port_iter->next();
     registerConcretePort(cur_port);
   }
-
-  delete lib_iter;
 }
 
 void dbNetwork::readDbNetlistAfter()
@@ -1894,7 +1892,8 @@ void dbNetwork::readLibertyAfter(LibertyLibrary* lib)
 {
   for (ConcreteLibrary* clib : library_seq_) {
     if (!clib->isLiberty()) {
-      ConcreteLibraryCellIterator* cell_iter = clib->cellIterator();
+      std::unique_ptr<ConcreteLibraryCellIterator> cell_iter{
+          clib->cellIterator()};
       while (cell_iter->hasNext()) {
         ConcreteCell* ccell = cell_iter->next();
         // Don't clobber an existing liberty cell so link points to the first.
@@ -1904,7 +1903,8 @@ void dbNetwork::readLibertyAfter(LibertyLibrary* lib)
             TestCell* test_cell = lcell->testCell();
             lcell->setExtCell(ccell->extCell());
             ccell->setLibertyCell(lcell);
-            ConcreteCellPortBitIterator* port_iter = ccell->portBitIterator();
+            std::unique_ptr<ConcreteCellPortBitIterator> port_iter{
+                ccell->portBitIterator()};
             while (port_iter->hasNext()) {
               ConcretePort* cport = port_iter->next();
               const char* port_name = cport->name();
@@ -1930,11 +1930,9 @@ void dbNetwork::readLibertyAfter(LibertyLibrary* lib)
                 }
               }
             }
-            delete port_iter;
           }
         }
       }
-      delete cell_iter;
     }
   }
 

src/dbSta/src/dbReadVerilog.cc

@@ -466,7 +466,8 @@ void Verilog2db::makeDbModule(
       }
     }
   }
-  InstanceChildIterator* child_iter = network_->childIterator(inst);
+  std::unique_ptr<InstanceChildIterator> child_iter{
+      network_->childIterator(inst)};
   while (child_iter->hasNext()) {
     Instance* child = child_iter->next();
     if (network_->isHierarchical(child)) {
@@ -539,7 +540,6 @@ void Verilog2db::makeDbModule(
       }
     }
   }
-  delete child_iter;
   if (module->getChildren().reversible()
       && module->getChildren().orderReversed()) {
     module->getChildren().reverse();
@@ -640,7 +640,7 @@ dbIoType Verilog2db::staToDb(PortDirection* dir)
 void Verilog2db::makeDbNets(const Instance* inst)
 {
   bool is_top = (inst == network_->topInstance());
-  NetIterator* net_iter = network_->netIterator(inst);
+  std::unique_ptr<NetIterator> net_iter{network_->netIterator(inst)};
   // Todo, put dbnets in the module in case of hierarchy (not block)
   while (net_iter->hasNext()) {
     Net* net = net_iter->next();
@@ -657,12 +657,12 @@ void Verilog2db::makeDbNets(const Instance* inst)
 
       // Sort connected pins for regression stability.
       PinSeq net_pins;
-      NetConnectedPinIterator* pin_iter = network_->connectedPinIterator(net);
+      std::unique_ptr<NetConnectedPinIterator> pin_iter{
+          network_->connectedPinIterator(net)};
       while (pin_iter->hasNext()) {
         const Pin* pin = pin_iter->next();
         net_pins.push_back(pin);
       }
-      delete pin_iter;
       sort(net_pins, PinPathNameLess(network_));
 
       for (const Pin* pin : net_pins) {
@@ -689,13 +689,13 @@ void Verilog2db::makeDbNets(const Instance* inst)
       }
     }
   }
-  delete net_iter;
-  InstanceChildIterator* child_iter = network_->childIterator(inst);
+
+  std::unique_ptr<InstanceChildIterator> child_iter{
+      network_->childIterator(inst)};
   while (child_iter->hasNext()) {
     const Instance* child = child_iter->next();
     makeDbNets(child);
   }
-  delete child_iter;
 }
 
 void Verilog2db::makeVModNets(
@@ -814,10 +814,8 @@ dbModNet* Verilog2db::constructModNet(Net* inst_pin_net, dbModule* module)
 
 bool Verilog2db::hasTerminals(Net* net) const
 {
-  NetTermIterator* term_iter = network_->termIterator(net);
-  bool has_terms = term_iter->hasNext();
-  delete term_iter;
-  return has_terms;
+  std::unique_ptr<NetTermIterator> term_iter{network_->termIterator(net)};
+  return term_iter->hasNext();
 }
 
 dbMaster* Verilog2db::getMaster(Cell* cell)

src/dbSta/src/dbSdcNetwork.cc

@@ -91,14 +91,14 @@ InstanceSeq dbSdcNetwork::findInstancesMatching(
 void dbSdcNetwork::findInstancesMatching1(const PatternMatch* pattern,
                                           InstanceSeq& insts) const
 {
-  InstanceChildIterator* child_iter = childIterator(topInstance());
+  std::unique_ptr<InstanceChildIterator> child_iter{
+      childIterator(topInstance())};
   while (child_iter->hasNext()) {
     Instance* child = child_iter->next();
     if (pattern->match(staToSdc(name(child)))) {
       insts.push_back(child);
     }
   }
-  delete child_iter;
 }
 
 NetSeq dbSdcNetwork::findNetsMatching(const Instance*,
@@ -129,14 +129,13 @@ NetSeq dbSdcNetwork::findNetsMatching(const Instance*,
 void dbSdcNetwork::findNetsMatching1(const PatternMatch* pattern,
                                      NetSeq& nets) const
 {
-  NetIterator* net_iter = netIterator(topInstance());
+  std::unique_ptr<NetIterator> net_iter{netIterator(topInstance())};
   while (net_iter->hasNext()) {
     Net* net = net_iter->next();
     if (pattern->match(staToSdc(name(net)))) {
       nets.push_back(net);
     }
   }
-  delete net_iter;
 }
 
 PinSeq dbSdcNetwork::findPinsMatching(const Instance* instance,
@@ -145,17 +144,15 @@ PinSeq dbSdcNetwork::findPinsMatching(const Instance* instance,
   PinSeq pins;
   if (stringEq(pattern->pattern(), "*")) {
     // Pattern of '*' matches all child instance pins.
-    InstanceChildIterator* child_iter = childIterator(instance);
+    std::unique_ptr<InstanceChildIterator> child_iter{childIterator(instance)};
     while (child_iter->hasNext()) {
       Instance* child = child_iter->next();
-      InstancePinIterator* pin_iter = pinIterator(child);
+      std::unique_ptr<InstancePinIterator> pin_iter{pinIterator(child)};
       while (pin_iter->hasNext()) {
         Pin* pin = pin_iter->next();
         pins.push_back(pin);
       }
-      delete pin_iter;
     }
-    delete child_iter;
   } else {
     char *inst_path, *port_name;
     pathNameLast(pattern->pattern(), inst_path, port_name);
@@ -188,7 +185,8 @@ void dbSdcNetwork::findMatchingPins(const Instance* instance,
         bool bus_matches
             = port_pattern->match(port_name)
               || port_pattern->match(escapeDividers(port_name, network_));
-        PortMemberIterator* member_iter = network_->memberIterator(port);
+        std::unique_ptr<PortMemberIterator> member_iter{
+            network_->memberIterator(port)};
         while (member_iter->hasNext()) {
           Port* member_port = member_iter->next();
           Pin* pin = network_->findPin(instance, member_port);
@@ -205,7 +203,6 @@ void dbSdcNetwork::findMatchingPins(const Instance* instance,
             }
           }
         }
-        delete member_iter;
       } else if (port_pattern->match(port_name)
                  || port_pattern->match(escapeDividers(port_name, network_))) {
         Pin* pin = network_->findPin(instance, port);

src/dbSta/src/dbSta.cc

@@ -536,17 +536,31 @@ void dbSta::report_cell_usage(odb::dbModule* module, const bool verbose)
                     module->getName());
   }
   logger_->report(header_format, "Cell type report:", "Count", "Area");
+
+  const std::regex regexp(" |/|-");
+  std::string metrics_suffix;
+  if (block->getTopModule() != module) {
+    metrics_suffix = fmt::format("__in_module:{}", module->getName());
+  }
+
   for (auto [type, stats] : instances_types) {
-    std::string type_name = getInstanceTypeText(type);
+    const std::string type_name = getInstanceTypeText(type);
     logger_->report(
         format, type_name, stats.count, stats.area / area_to_microns);
     total_area += stats.area;
 
-    std::regex regexp(" |/|-");
-    logger_->metric("design__instance__count__class:"
-                        + toLowerCase(regex_replace(type_name, regexp, "_")),
+    const std::string type_class
+        = toLowerCase(regex_replace(type_name, regexp, "_"));
+    const std::string metric_suffix = type_class + metrics_suffix;
+
+    logger_->metric("design__instance__count__class:" + metric_suffix,
                     stats.count);
+    logger_->metric("design__instance__area__class:" + metric_suffix,
+                    stats.area / area_to_microns);
   }
+  logger_->metric("design__instance__count" + metrics_suffix, total_usage);
+  logger_->metric("design__instance__area" + metrics_suffix,
+                  total_area / area_to_microns);
   logger_->report(format, "Total", total_usage, total_area / area_to_microns);
 
   if (verbose) {

src/dbSta/test/regression_tests.tcl

@@ -35,6 +35,7 @@ record_tests {
 
   report_cell_usage
   report_cell_usage_modinsts
+  report_cell_usage_modinsts_metrics
 
   write_verilog1
   write_verilog2

src/dbSta/test/report_cell_usage_modinsts_metrics.jsonok

@@ -0,0 +1,20 @@
+{
+	"design__instance__count__class:buffer": 4,
+	"design__instance__area__class:buffer": 4000,
+	"design__instance__count__class:sequential_cell": 2,
+	"design__instance__area__class:sequential_cell": 2000,
+	"design__instance__count": 6,
+	"design__instance__area": 6000,
+	"design__instance__count__class:buffer__in_module:block1": 2,
+	"design__instance__area__class:buffer__in_module:block1": 2000,
+	"design__instance__count__class:sequential_cell__in_module:block1": 1,
+	"design__instance__area__class:sequential_cell__in_module:block1": 1000,
+	"design__instance__count__in_module:block1": 3,
+	"design__instance__area__in_module:block1": 3000,
+	"design__instance__count__class:buffer__in_module:block1-1": 2,
+	"design__instance__area__class:buffer__in_module:block1-1": 2000,
+	"design__instance__count__class:sequential_cell__in_module:block1-1": 1,
+	"design__instance__area__class:sequential_cell__in_module:block1-1": 1000,
+	"design__instance__count__in_module:block1-1": 3,
+	"design__instance__area__in_module:block1-1": 3000
+}

src/dbSta/test/report_cell_usage_modinsts_metrics.ok

@@ -0,0 +1,28 @@
+[INFO ODB-0227] LEF file: liberty1.lef, created 2 layers, 6 library cells
+Cell type report:                       Count       Area
+  Buffer                                    4    4000.00
+  Sequential cell                           2    2000.00
+  Total                                     6    6000.00
+
+Cell instance report:
+  snl_bufx1                                 4    4000.00
+  snl_ffqx1                                 2    2000.00
+Cell type report for b1 (block1)
+Cell type report:                       Count       Area
+  Buffer                                    2    2000.00
+  Sequential cell                           1    1000.00
+  Total                                     3    3000.00
+
+Cell instance report:
+  snl_bufx1                                 2    2000.00
+  snl_ffqx1                                 1    1000.00
+Cell type report for b2 (block1-1)
+Cell type report:                       Count       Area
+  Buffer                                    2    2000.00
+  Sequential cell                           1    1000.00
+  Total                                     3    3000.00
+
+Cell instance report:
+  snl_bufx1                                 2    2000.00
+  snl_ffqx1                                 1    1000.00
+No differences found.

src/dbSta/test/report_cell_usage_modinsts_metrics.tcl

@@ -0,0 +1,20 @@
+# Report cell usage for modinsts with metrics
+
+source "helpers.tcl"
+read_lef liberty1.lef
+read_liberty liberty1.lib
+read_verilog hier1.v
+link_design top
+
+set metrics [make_result_file report_cell_usage_modinsts_metrics.json]
+
+utl::open_metrics $metrics
+
+report_cell_usage -verbose
+
+report_cell_usage -verbose b1
+report_cell_usage -verbose b2
+
+utl::close_metrics $metrics
+
+diff_files report_cell_usage_modinsts_metrics.jsonok $metrics

src/grt/README.md

@@ -117,7 +117,7 @@ set_global_routing_layer_adjustment layer adjustment
 
 | Argument Name | Description | 
 | ----- | ----- |
-| `layer` | Integer for the layer number (e.g. for M1 you would use 1). |
+| `layer` | String for the layer name. |
 | `adjustment` | Float indicating the percentage reduction of each edge in the specified layer. |
 
 
@@ -138,7 +138,7 @@ set_global_routing_region_adjustment
 | Switch Name | Description |
 | ----- | ----- |
 | `lower_left_x`, `lower_left_y`, `upper_right_x` , `upper_right_y` | Bounding box to consider. |
-| `-layer` | Integer for the layer number (e.g. for M1 you would use 1). |
+| `-layer` | String for the layer name. |
 | `-adjustment` | Float indicating the percentage reduction of each edge in the specified layer. |
 
 ### Set Global Routing Randomness

src/grt/src/GlobalRouter.tcl

@@ -103,17 +103,19 @@ proc set_global_routing_region_adjustment { args } {
     sta::check_positive_float "lower_left_y" $lower_y
     sta::check_positive_float "upper_right_x" $upper_x
     sta::check_positive_float "upper_right_y" $upper_y
-    sta::check_positive_integer "-layer" $layer
     sta::check_positive_float "-adjustment" $adjustment
 
+    set layer_idx [grt::parse_layer_name $layer]
+    grt::check_routing_layer $layer_idx
+
     set lower_x [expr { int($lower_x * $lef_units) }]
     set lower_y [expr { int($lower_y * $lef_units) }]
     set upper_x [expr { int($upper_x * $lef_units) }]
     set upper_y [expr { int($upper_y * $lef_units) }]
 
     grt::check_region $lower_x $lower_y $upper_x $upper_y
 
-    grt::add_region_adjustment $lower_x $lower_y $upper_x $upper_y $layer $adjustment
+    grt::add_region_adjustment $lower_x $lower_y $upper_x $upper_y $layer_idx $adjustment
   } else {
     utl::error GRT 50 \
       "Command set_global_routing_region_adjustment needs four arguments\

src/grt/test/region_adjustment.tcl

@@ -3,7 +3,7 @@ source "helpers.tcl"
 read_lef "Nangate45/Nangate45.lef"
 read_def "region_adjustment.def"
 
-set_global_routing_region_adjustment {1.4 2 20 15.5} -layer 2 -adjustment 0.9
+set_global_routing_region_adjustment {1.4 2 20 15.5} -layer metal2 -adjustment 0.9
 
 set guide_file [make_result_file region_adjustment.guide]