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dpl: update metrics
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Signed-off-by: Lucas Yuki Imamura <[email protected]>
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@LucasYuki
LucasYuki committed Feb 11, 2025
1 parent dca0eee commit b844e5f
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Showing 45 changed files with 53,579 additions and 53,589 deletions.
4 changes: 2 additions & 2 deletions src/cts/test/array.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -68,11 +68,11 @@
[INFO RSZ-0048] Inserted 91 buffers in 31 nets.
Placement Analysis
---------------------------------
total displacement 3286.3 u
total displacement 3281.3 u
average displacement 1.1 u
max displacement 117.1 u
original HPWL 132659.6 u
legalized HPWL 133128.8 u
legalized HPWL 133126.9 u
delta HPWL 0 %

Clock clk
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4 changes: 2 additions & 2 deletions src/cts/test/array_ins_delay.ok
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Expand Up @@ -120,11 +120,11 @@
[INFO RSZ-0048] Inserted 108 buffers in 50 nets.
Placement Analysis
---------------------------------
total displacement 4686.3 u
total displacement 4682.9 u
average displacement 1.5 u
max displacement 153.0 u
original HPWL 182322.8 u
legalized HPWL 183136.4 u
legalized HPWL 183155.3 u
delta HPWL 0 %

Clock clk
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4 changes: 2 additions & 2 deletions src/cts/test/array_no_blockages.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -68,11 +68,11 @@
[INFO RSZ-0048] Inserted 90 buffers in 31 nets.
Placement Analysis
---------------------------------
total displacement 2522.3 u
total displacement 2522.4 u
average displacement 0.9 u
max displacement 117.9 u
original HPWL 132665.1 u
legalized HPWL 133068.4 u
legalized HPWL 133067.8 u
delta HPWL 0 %

Clock clk
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2 changes: 1 addition & 1 deletion src/cts/test/simple_test_hier.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ delta HPWL 0 %
[INFO CTS-0098] Clock net "clk"
[INFO CTS-0099] Sinks 17
[INFO CTS-0100] Leaf buffers 0
[INFO CTS-0101] Average sink wire length 23.08 um
[INFO CTS-0101] Average sink wire length 22.90 um
[INFO CTS-0102] Path depth 2 - 2
[INFO CTS-0207] Leaf load cells 1
No differences found.
48 changes: 21 additions & 27 deletions src/cts/test/simple_test_hier_out.vok
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Original file line number Diff line number Diff line change
Expand Up @@ -9,29 +9,25 @@ module test_16_sinks (clk);
.Z(clknet_1_0__leaf_clk));
CLKBUF_X3 clkbuf_0_clk (.A(clk),
.Z(clknet_0_clk));
flop_pair U1 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair U1 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U2 U2 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U3 U3 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U4 U4 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U5 U5 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U6 U6 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U7 U7 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
flop_pair_U5 U5 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
flop_pair_U6 U6 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U7 U7 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
endmodule
module flop_pair (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
input clknet_1_1__leaf_clk_i;
module flop_pair (clknet_1_0__leaf_clk_i);
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
endmodule
module flop_pair_U2 (clknet_1_1__leaf_clk_i,
Expand All @@ -40,17 +36,17 @@ module flop_pair_U2 (clknet_1_1__leaf_clk_i,
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
endmodule
module flop_pair_U3 (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
input clknet_1_1__leaf_clk_i;
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
endmodule
module flop_pair_U4 (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
Expand All @@ -61,11 +57,13 @@ module flop_pair_U4 (clknet_1_1__leaf_clk_i,
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
endmodule
module flop_pair_U5 (clknet_1_0__leaf_clk_i);
module flop_pair_U5 (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
input clknet_1_1__leaf_clk_i;
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
endmodule
module flop_pair_U6 (clknet_1_1__leaf_clk_i,
Expand All @@ -74,24 +72,20 @@ module flop_pair_U6 (clknet_1_1__leaf_clk_i,
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
endmodule
module flop_pair_U7 (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
input clknet_1_1__leaf_clk_i;
module flop_pair_U7 (clknet_1_0__leaf_clk_i);
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
endmodule
module flop_pair_U8 (clknet_1_1__leaf_clk_i,
clknet_1_0__leaf_clk_i);
module flop_pair_U8 (clknet_1_1__leaf_clk_i);
input clknet_1_1__leaf_clk_i;
input clknet_1_0__leaf_clk_i;


DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
endmodule
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