pointer logic instructions

MESYETI · Nov 15, 2023 · ca0a0b7 · ca0a0b7
1 parent c787ac5
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diff --git a/docs/architecture.md b/docs/architecture.md
@@ -91,4 +91,14 @@ registers, words (16-bit) for data, and 24-bit values for addresses
 - `WRBB (reg pair) (reg)` (0x31) - Writes the low 8-bits of `reg` to `BS` + reg pair
 - `WRWB (reg pair) (reg)` (0x32) - Writes `reg` to `BS` + reg pair
 - `WRAB (reg pair) (reg pair)` (0x33) - Writes the second reg pair to `BS` + second reg pair
+- `LT (reg) (reg)` (0x34) - Sets `A` to 65535 if the first register is less than the
+                            second register, and 0 if it isn't
+- `GT (reg) (reg)` (0x35) - Sets `A` to 65535 if the first register is greater than the
+                            second register, and 0 if it isn't
+- `CMPP (reg pair) (reg pair)` (0x36) - Sets `A` to 65535 if the reg pairs are equal,
+                                        and 0 if they aren't
+- `LTP (reg pair) (reg pair)` (0x37) - Sets `A` to 65535 if the first reg pair is less
+                                       than the second, and 0 if it isn't
+- `GTP (reg pair) (reg pair)` (0x38) - Sets `A` to 65535 if the first reg pair is greater
+                                       than the second, and 0 if it isn't
 - `HLT` (0xFF) - Stops execution
diff --git a/source/assembler/assembler.d b/source/assembler/assembler.d
@@ -87,6 +87,11 @@ class Assembler {
 		AddInstruction("wrbb", Opcode.WRBB, [Param.RegisterPair, Param.Register]);
 		AddInstruction("wrwb", Opcode.WRWB, [Param.RegisterPair, Param.Register]);
 		AddInstruction("wrab", Opcode.WRAB, [Param.RegisterPair, Param.RegisterPair]);
+		AddInstruction("lt",   Opcode.LT,   [Param.Register, Param.Register]);
+		AddInstruction("gt",   Opcode.GT,   [Param.Register, Param.Register]);
+		AddInstruction("cmpp", Opcode.CMPP, [Param.RegisterPair, Param.RegisterPair]);
+		AddInstruction("gtp",  Opcode.GTP, [Param.RegisterPair, Param.RegisterPair]);
+		AddInstruction("ltp",  Opcode.LTP, [Param.RegisterPair, Param.RegisterPair]);
 		AddInstruction("hlt",  Opcode.HLT,  []);
 
 		// special

diff --git a/source/computer.d b/source/computer.d
@@ -70,6 +70,11 @@ enum Opcode {
 	WRBB = 0x31,
 	WRWB = 0x32,
 	WRAB = 0x33,
+	LT   = 0x34,
+	GT   = 0x35,
+	CMPP = 0x36,
+	LTP  = 0x37,
+	GTP  = 0x38,
 	HLT  = 0xFF
 }
 
@@ -696,6 +701,36 @@ class Computer {
 				WriteAddr(bs + addr, value);
 				break;
 			}
+			case Opcode.LT: {
+				auto v1 = ReadReg(NextByte());
+				auto v2 = ReadReg(NextByte());
+				a       = v1 < v2? 0xFFFF : 0;
+				break;
+			}
+			case Opcode.GT: {
+				auto v1 = ReadReg(NextByte());
+				auto v2 = ReadReg(NextByte());
+				a       = v1 > v2? 0xFFFF : 0;
+				break;
+			}
+			case Opcode.CMPP: {
+				auto v1 = ReadRegPair(NextByte());
+				auto v2 = ReadRegPair(NextByte());
+				a       = v1 == v2? 0xFFFF : 0;
+				break;
+			}
+			case Opcode.LTP: {
+				auto v1 = ReadRegPair(NextByte());
+				auto v2 = ReadRegPair(NextByte());
+				a       = v1 < v2? 0xFFFF : 0;
+				break;
+			}
+			case Opcode.GTP: {
+				auto v1 = ReadRegPair(NextByte());
+				auto v2 = ReadRegPair(NextByte());
+				a       = v1 > v2? 0xFFFF : 0;
+				break;
+			}
 			case Opcode.HLT: {
 				halted = true;
 				break;