Skip to content

Issues: MIPT-ILab/mipt-mips

39 Open 175 Closed
39 Open 175 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Adopt Clang-Format 4 Features of medium complexity which usually require infrastructure enhancements. good first issue Good task to start with MIPT-MIPS development infrastructure Improves build/CI infrastructure. S1 — Infrastructure To solve the issue, you need knowledge about CMake, build procedure, Travis CI etc.
#1517 opened Feb 13, 2022 by pavelkryukov
4 tasks
Deliver unit tests for JSON output 2 Small features, tests coverage, simple laboratory works S1 — C++ To solve the issue, you barely need knowledge about CPU microarchitecture, just C++ coding. testing Improves testing coverage
#1453 opened Feb 8, 2021 by pavelkryukov
External register writes should flush pipeline 3 Features of medium complexity or infrastructure enhancements bug Fixes a bug or potential bug in simulation. S1 — Pipeline To solve the issue, you need knowledge about pipeline, data bypass, scoreboarding
#1311 opened Apr 17, 2020 by pavelkryukov
Make statistic dump better 3 Features of medium complexity or infrastructure enhancements infrastructure Improves build/CI infrastructure. S1 — Pipeline To solve the issue, you need knowledge about pipeline, data bypass, scoreboarding
#1267 opened Mar 18, 2020 by pavelkryukov
Verify correctness of read-after-write behavior 1 Usually one-liner tasks, but may require some deep into infrastructure. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA testing Improves testing coverage
#1266 opened Mar 18, 2020 by pavelkryukov
Implement RV64 bit manipulation instructions on 32-bit registers 3 Features of medium complexity or infrastructure enhancements enhancement Adds a new feature to simulation. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#1157 opened Nov 17, 2019 by pavelkryukov
Implement remaining RISC-V B instructions 2 Small features, tests coverage, simple laboratory works enhancement Adds a new feature to simulation. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#1095 opened Sep 29, 2019 by pavelkryukov
2
Adjust Fetch/Target prediction to support RISC-V compressed instructions 4 Features of medium complexity which usually require infrastructure enhancements. enhancement Adds a new feature to simulation. S1 — Branch prediction To solve the issue, you need knowledge about branch prediction
#1076 opened May 18, 2019 by pavelkryukov
Implement big-endian MIPS unaligned load/stores 2 Small features, tests coverage, simple laboratory works enhancement Adds a new feature to simulation. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#1044 opened May 12, 2019 by pavelkryukov
Add MIPS-style TLB to functional simulation 4 Features of medium complexity which usually require infrastructure enhancements. enhancement Adds a new feature to simulation. S2 — Caches To solve the issue, you NEED knowledge about caches. OOO hierarchy etc.
#1000 opened May 3, 2019 by pavelkryukov Run DOOM2 on Nintendo64 model
Describe simulation of BP and BTB pipelines 3 Features of medium complexity or infrastructure enhancements documentations Adds a new manual to Wiki. S1 — Branch prediction To solve the issue, you need knowledge about branch prediction
#997 opened May 2, 2019 by pavelkryukov
18
Support RISC-V Proxy Kernel 6 New functionality which has to be built from scratch. enhancement Adds a new feature to simulation. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#920 opened Mar 15, 2019 by pavelkryukov
Rearrange data bypass to have Decode stage 3 Features of medium complexity or infrastructure enhancements code Enhances infrastructure or refines, Requires almost no knowledge in CPU microarchitecture. S1 — Pipeline To solve the issue, you need knowledge about pipeline, data bypass, scoreboarding
#823 opened Feb 8, 2019 by pavelkryukov
3
Add tests to GDBWrapper class 2 Small features, tests coverage, simple laboratory works S1 — C++ To solve the issue, you barely need knowledge about CPU microarchitecture, just C++ coding. testing Improves testing coverage
#764 opened Jan 23, 2019 by pavelkryukov
Add unit tests for bypass module 3 Features of medium complexity or infrastructure enhancements good first issue Good task to start with MIPT-MIPS development S1 — Pipeline To solve the issue, you need knowledge about pipeline, data bypass, scoreboarding testing Improves testing coverage
#716 opened Nov 23, 2018 by pavelkryukov
9
Implement delayed branches in PerfSim 5 Same as 4, but requires good understanding of CPU microarchitecture. bug Fixes a bug or potential bug in simulation. S1 — Branch prediction To solve the issue, you need knowledge about branch prediction
#639 opened Oct 12, 2018 by pavelkryukov
3 tasks
Run DOOM2 on Nintendo64 model
Implement interrupts 5 Same as 4, but requires good understanding of CPU microarchitecture. enhancement Adds a new feature to simulation. S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#604 opened Oct 5, 2018 by pavelkryukov Run DOOM2 on Nintendo64 model
Implement hardware watchpoint 2 Small features, tests coverage, simple laboratory works enhancement Adds a new feature to simulation. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#591 opened Oct 1, 2018 by pavelkryukov
Add loop interchange example trace 2 Small features, tests coverage, simple laboratory works S2 — Caches To solve the issue, you NEED knowledge about caches. OOO hierarchy etc. testing Improves testing coverage
#579 opened Sep 27, 2018 by pavelkryukov
Add MIPS assembler software prefetch example 2 Small features, tests coverage, simple laboratory works S2 — Caches To solve the issue, you NEED knowledge about caches. OOO hierarchy etc. testing Improves testing coverage
#578 opened Sep 27, 2018 by pavelkryukov
Add nested loops example in MIPS assembler 1 Usually one-liner tasks, but may require some deep into infrastructure. good first issue Good task to start with MIPT-MIPS development S1 — Branch prediction To solve the issue, you need knowledge about branch prediction testing Improves testing coverage
#577 opened Sep 27, 2018 by pavelkryukov
2
Perform cache line size study with variable cache miss latency 2 Small features, tests coverage, simple laboratory works laboratory Adds a new study report to Wiki. S2 — Caches To solve the issue, you NEED knowledge about caches. OOO hierarchy etc.
#555 opened Sep 3, 2018 by pavelkryukov
Finish 'How to debug MIPT-MIPS using GDB' manual 1 Usually one-liner tasks, but may require some deep into infrastructure. documentations Adds a new manual to Wiki. good first issue Good task to start with MIPT-MIPS development S1 — ISA To solve the issue, you need knowledge about MIPS or RISC-V ISA
#525 opened Jul 28, 2018 by pavelkryukov
31
Add wiki page about factory patterns 3 Features of medium complexity or infrastructure enhancements documentations Adds a new manual to Wiki. S1 — C++ To solve the issue, you barely need knowledge about CPU microarchitecture, just C++ coding.
#493 opened Jul 22, 2018 by pavelkryukov
2
Implement second level cache 5 Same as 4, but requires good understanding of CPU microarchitecture. enhancement Adds a new feature to simulation. S2 — Caches To solve the issue, you NEED knowledge about caches. OOO hierarchy etc.
#490 opened Jul 21, 2018 by pavelkryukov
ProTip! Adding no:label will show everything without a label.