Introduction
WebRISC-V is a graphical processor simulator and assembly code editor built for the RISC-V instruction set architecture, suitable for teaching how assembly level code is executed on various microarchitectures.
The following sections serve as an introduction to the main features of WebRISC-V.
The header within WebRISC-V contains all of the relevant actions for controlling the simulator.
- Load Programs: Switch to the Editor Commands and open the Editor Panel.
- Pipeline in New Window: Open the pipeline schema by itself in a new window.
- System Reset: Reset the simulator state.
- Execute All: In case of loaded program, execute all the instructions.
- Step Forward: In case of loaded program, proceed to the next clock cycle.
- Step Back: In case of loaded program, return to the previous clock cycle.
- Example List: Load into the Assembly Editor one of the sample programs.
- Clear Textbox: Clear the Assembly Editor.
- Load into Memory: Assemble the directives and instructions in the Assembly editor for execution.
- Return to pipeline: Switch to the Schema Commands and open the Schema Panel.
- Architecture: Choose the ISA of the pipeline.
- Forwarding: Choose if the pipeline uses forwarding.
- Branch Hazard Handling: Choose if the pipeline flushes or executes the instruction after a control hazard.
- Popup Elements on Hover: Choose if the pipeline schema should visualize its architecural elements on hover.
- Show Data Path: Choose if the pipeline schema should show the data wires.
- Show Control Path: Choose if the pipeline schema should show the control wires.
- Data Memory: Choose to visualize the Data Memory addresses ordered from Lower to Upper bytes or viceversa.
WebRISC-V displays the execution state, such as the current cycle of the execution and the state of the pipeline stages. It also displays buttons for opening other execution relevant panels:
- Execution Table
- Console
The instruction memory tab provides a view of the assembled instructions. It shows their memory address, type and structural components. During execution, it also displays the current stage and state of the instructions.
The data memory tab provides a view into the entire addressable address space. Navigating the memory may be done through the display of the entire Data memory, of a segment of the memory, or a selected range of memory addresses.
The registers tab provides a view into the entire register file.
The editor panel displays on the left a simple manual for the selected Architecture.
It details and explains the available instructions, directives and syscalls.
WebRISC-V is bundled with simple examples of RISC-V assembly programs, which can be found at the Example List command.
The schema panel is where WebRISC-V displays its view of the currently selected pipeline, as well as additional information relevant to its architectural elements.
WebRISC-V includes the possibility of displaying a chart showing which instructions resided in which pipeline stage for each cycle.
Here we introduced a practical way to visualize the loop case by automatically squashing the cycles of the loop in the diagram, but without losing the precise accounting of the executed cycles.
This makes for easier comparisons with pencil-and-paper approaches.
WebRISC-V includes an I/O console that, in case of the relevant syscalls, permits input or displays output.