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Arslan Ali edited this page Nov 28, 2019 · 2 revisions

Welcome to the FPGA-Vertex-6-GTx-Interface wiki!

Serial communication between two Vertex 6 FPGA using vertex 6 GTx IP core. Simulation is done in Xilinx ISE 14.1 simualtor. Output waveforms are in the steps folder.

To Run First change the directory to /vertex6_gtx_tx_component/simulation/functional/ Then in Xilinx ISE Cmd type. ./simulate_isim.sh

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