Glossar

• component: the component placed in TC, excluding inputs/outputs
• submodule: the verilog counterpart to a component: There might be submodules without a component, and components without a submodule
• UUID: A numeric identifier to know the relation between a component and a submodule
• (display) name: A nice named tied to a UUID
• (tc2v) compiler: the python code taking in TC save files and outputting verilog
• (verilog) synthesizer: the (third party) software taking in the generated verilog and puts it onto an FPGA
• (verilog) (sim) compiler: the (third party) software taking in the generated verilog and generating a simulator from it
• simulator: The piece of code simulating verilog when running on a PC and connecting to an emulator
• synth: The context when the verilog has been compiled to FPGA
• sim: The context when verilog is running on a simulator
• emu(lator): A software that provides a server for simulators to connect to
• component mapping: A file for emulators and synth that maps UUIDs to display names
• pin mapping: A file for emulators and synth that maps display names to FPGA outputs
• display mapping: a file, specifically for emulators that maps display names to visual components