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@yilin-void yilin-void commented Aug 21, 2025

Summary by CodeRabbit

  • New Features
    • GPU-accelerated per-token FP4 global-scale calculation added; supports FP16 and BF16 inputs, optional tokens-per-batch masking, and a PyTorch operator used in low-precision MoE combine flow.
  • Performance
    • Native operator replaces Python-side reduction, improving throughput for FP4 quantization and enabling vectorized reductions for larger hidden sizes.
  • Tests
    • New unit tests for correctness across shapes/dtypes, masked tokens, performance timing, and input validation.

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@yilin-void yilin-void requested a review from a team as a code owner August 21, 2025 10:14
@yilin-void yilin-void requested a review from yuxianq August 21, 2025 10:14
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coderabbitai bot commented Aug 21, 2025

📝 Walkthrough

Walkthrough

Adds an additive FP4 per-token global-scale computation: a vectorized templated CUDA kernel + host launcher (FP16/BF16), header declaration, C++/PyTorch binding (trtllm.calculate_nvfp4_global_scale), Python integration in fused_moe_wide_ep, and unit tests and a Python custom-op stub.

Changes

Cohort / File(s) Summary
CUDA kernel & header
cpp/tensorrt_llm/kernels/quantization.cu, cpp/tensorrt_llm/kernels/quantization.h
Adds vectorized utilities, computePerTokenGlobalScaleForFP4QuantizationKernel<T> and host launcher computePerTokenGlobalScaleForFP4Quantization<T>; computes per-token max-abs and writes globalScale[token] = 2688.0f / maxAbs. Adds alignment checks and explicit instantiations for half and __nv_bfloat16, and a template declaration in the header.
C++ PyTorch extension
cpp/tensorrt_llm/thop/fp4Quantize.cpp, cpp/tensorrt_llm/thop/fp4Quantize.h
Adds calculate_nvfp4_global_scale(at::Tensor, optional tokensPerBatch) -> at::Tensor; dispatches by dtype (FP16/BF16 with guard), queries SM count, calls the CUDA host launcher, and registers the op via TORCH_LIBRARY/TORCH_LIBRARY_IMPL.
Python integration
tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py
Replaces manual (448*6/max_abs) Python per-token scaling with torch.ops.trtllm.calculate_nvfp4_global_scale(final_hidden_states, recv_expert_count) under use_low_precision_combine; downstream usage unchanged.
Unit tests
tests/unittest/_torch/thop/test_fp4_calculate_global_scale.py
Adds tests comparing operator output to reference (per-token max-abs then (448*6)/maxAbs), masked tokens_per_batch handling, performance timing, and invalid-input checks across shapes and dtypes (FP16/BF16).
Python custom-op stub
tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py
Adds a fake Python op trtllm::calculate_nvfp4_global_scale returning a float32 tensor with last dim = 1 for non-CUDA/backstop usage.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  actor Python as fused_moe_wide_ep
  participant Op as trtllm.calculate_nvfp4_global_scale
  participant Cpp as torch_ext (C++ binding)
  participant Host as HostWrapper computePerTokenGlobalScaleForFP4Quantization<T>
  participant Kernel as CUDA kernel
  participant GS as globalScale buffer

  Python->>Op: call(input, tokensPerBatch?)
  Op->>Cpp: dispatch by dtype, validate shapes
  Cpp->>Host: launch(b,m,n,input,tokensPerBatch,globalScale,SMcount,stream)
  Host->>Kernel: <<<grid,block>>> computePerTokenGlobalScaleForFP4QuantizationKernel<T>
  Kernel->>GS: reduce per-token maxAbs → write scale = 2688.0f / maxAbs
  Kernel-->>Host: done
  Host-->>Cpp: return globalScale tensor
  Cpp-->>Op: return at::Tensor
  Op-->>Python: use globalScale in low_latency_combine_fp4
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Estimated code review effort

🎯 4 (Complex) | ⏱️ ~60 minutes

Possibly related PRs

Suggested reviewers

  • yuxianq
  • yuantailing
  • litaotju
  • chenfeiz0326

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📒 Files selected for processing (5)
  • cpp/tensorrt_llm/kernels/quantization.cu (3 hunks)
  • cpp/tensorrt_llm/kernels/quantization.h (1 hunks)
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cpp/tensorrt_llm/kernels/quantization.cu (2)

406-408: Half specialization instantiation looks good

Explicit instantiation for half ensures the new path is linked even when only used from other TUs. No issues.


417-419: BF16 specialization instantiation is correctly gated

Instantiation under ENABLE_BF16 is consistent with the rest of the file. Once the VecTypeImpl guard is added (above), this remains coherent.

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@yilin-void yilin-void force-pushed the dev/fp4_global_scale branch from 7f80217 to 0f0f0e5 Compare August 21, 2025 10:17
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@yilin-void yilin-void requested a review from hyukn August 21, 2025 10:19
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Actionable comments posted: 4

🧹 Nitpick comments (9)
cpp/tensorrt_llm/kernels/quantization.h (2)

91-94: Add API contract (shape, dtype, semantics) to the new declaration.

Please document constraints clearly (rank 2/3, hidden_size multiple of 16, supported input dtypes, tokensPerBatch semantics and dtype). This avoids mismatches between callers and the .cu implementation.

Proposed header doc right above the declaration:

+//! Compute per-token NVFP4 global scales.
+//! Input:
+//!   - b: batch size (1 for [token_num, hidden_size], or batch for [batch, token_num, hidden_size]).
+//!   - m: token_num per batch (uniform upper bound when tokensPerBatch is provided).
+//!   - n: hidden_size, must be divisible by 16.
+//!   - input: device pointer to {half|__nv_bfloat16}, contiguous.
+//!   - tokensPerBatch: optional device pointer to int32 of length b; tokensPerBatch[i] in [0, m].
+//! Output:
+//!   - globalScale: device pointer to float32 with shape [b, m, 1] (or [m, 1] when b == 1).
+//! Stream:
+//!   - stream on which the kernel is launched.
 template <typename T>
 void computePerTokenGlobalScaleForFP4Quantization(int b, int m, int n, T const* input, int const* tokensPerBatch,
     float* globalScale, int multiProcessorCount, cudaStream_t stream = 0);

91-94: Consider int32_t for dimension parameters for cross-platform consistency.

Most kernels take int32-sized dims; using int32_t for b/m/n may reduce implicit casts at call sites and inside kernels.

tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (1)

692-694: Great swap-in of the CUDA op; add a lightweight guard for dtype and operator availability.

The CUDA op supports fp16/bf16 only. If final_hidden_states ever becomes fp32 here, the call will throw. Also, when the extension isn’t loaded (e.g., custom builds), we can fall back to the reference formula.

Patch:

-                    global_scales = torch.ops.trtllm.calculate_nvfp4_global_scale(
-                        final_hidden_states, recv_expert_count)
+                    # Ensure supported dtype (operator expects fp16/bf16)
+                    assert final_hidden_states.dtype in (torch.float16, torch.bfloat16), \
+                        f"calculate_nvfp4_global_scale expects fp16/bf16, got {final_hidden_states.dtype}"
+                    try:
+                        global_scales = torch.ops.trtllm.calculate_nvfp4_global_scale(
+                            final_hidden_states, recv_expert_count)
+                    except (RuntimeError, AttributeError) as e:
+                        # Fallback to Python reference if the op is unavailable
+                        max_abs = final_hidden_states.abs().amax(dim=-1, keepdim=True).to(torch.float32)
+                        global_scales = (448 * 6) / max_abs
cpp/tensorrt_llm/thop/fp4Quantize.h (1)

30-31: Document the new public API signature and expectations.

Please add a short Doxygen-style comment to clarify accepted ranks, dtype, shape of the returned tensor, and tokensPerBatch dtype/shape. This improves discoverability and prevents misuse.

Suggested header comment:

- at::Tensor calculate_nvfp4_global_scale(at::Tensor const& input, std::optional<at::Tensor> const& tokensPerBatch);
+//! Calculate NVFP4 per-token global scales.
+//! input: [token_num, hidden] or [batch, token_num, hidden], dtype: fp16/bf16, contiguous, hidden % 16 == 0
+//! tokensPerBatch (optional): 1D int32 tensor of length batch; tokensPerBatch[i] in [0, token_num]
+//! Returns: same leading dims as input with last dim = 1, dtype float32
+at::Tensor calculate_nvfp4_global_scale(at::Tensor const& input, std::optional<at::Tensor> const& tokensPerBatch);
tests/unittest/_torch/thop/test_fp4_calculate_global_scale.py (3)

25-29: Match reference formula with in-code constant; consider naming a constant.

The repeated literal (448 * 6) would be clearer as a named constant to convey meaning (e.g., kNVFP4_SCALE_NUMERATOR).

-def reference_calculate_global_scale(input_tensor):
+NVFP4_SCALE_NUMERATOR = 448 * 6
+
+def reference_calculate_global_scale(input_tensor):
     max_abs_values = input_tensor.abs().max(dim=-1, keepdim=True).values.to(
         torch.float32)
-    global_scales = (448 * 6) / max_abs_values
+    global_scales = NVFP4_SCALE_NUMERATOR / max_abs_values
     return global_scales

93-100: Fix long line flagged by Ruff and avoid dumping massive tensors on failure.

The assert message exceeds 120 chars and printing full tensors harms readability/perf.

-        torch.testing.assert_close(
-            custom_result,
-            reference_result,
-            atol=1e-3,
-            rtol=1e-3,
-            msg=
-            f"Shape: {input_shape}, dtype: {dtype}, custom_result: {custom_result}, reference_result: {reference_result}"
-        )
+        torch.testing.assert_close(
+            custom_result,
+            reference_result,
+            atol=1e-3,
+            rtol=1e-3,
+            msg=f"Mismatch for shape={input_shape}, dtype={dtype}"
+        )

171-219: Add negative tests for tokensPerBatch dtype, device mismatch, and out-of-range values.

The CUDA entry point currently doesn’t validate tokensPerBatch dtype/device/range; add tests to pin the expected behavior.

Proposed additions inside test_calculate_nvfp4_global_scale_invalid_inputs:

@@
     def test_calculate_nvfp4_global_scale_invalid_inputs(self):
@@
         with self.assertRaises(Exception):
             torch.ops.trtllm.calculate_nvfp4_global_scale(
                 input_tensor, tokens_per_batch)
 
+        # Wrong dtype for tokensPerBatch (int64 instead of int32)
+        input_tensor = torch.randn((4, 32, 4096), dtype=torch.float16, device='cuda')
+        tokens_per_batch = torch.randint(1, 33, (4,), device='cuda', dtype=torch.int64)
+        with self.assertRaises(Exception):
+            torch.ops.trtllm.calculate_nvfp4_global_scale(input_tensor, tokens_per_batch)
+
+        # tokensPerBatch on a different device (if multiple GPUs are available)
+        if torch.cuda.device_count() >= 2:
+            input_tensor = input_tensor.to('cuda:0')
+            tokens_per_batch = torch.randint(1, 33, (4,), device='cuda:1', dtype=torch.int32)
+            with self.assertRaises(Exception):
+                torch.ops.trtllm.calculate_nvfp4_global_scale(input_tensor, tokens_per_batch)
+
+        # tokensPerBatch values out of range
+        input_tensor = torch.randn((4, 32, 4096), dtype=torch.float16, device='cuda')
+        tokens_per_batch = torch.tensor([0, 32, 65, -1], device='cuda', dtype=torch.int32)  # includes > max and negative
+        with self.assertRaises(Exception):
+            torch.ops.trtllm.calculate_nvfp4_global_scale(input_tensor, tokens_per_batch)

I can follow up with matching validation in the CUDA binding.

cpp/tensorrt_llm/thop/fp4Quantize.cpp (1)

238-251: Bindings look correct. Consider registering a CPU stub that throws a clearer error.

When called on CPU tensors, the operator currently fails the CUDA checks. A CPU backend that throws a NotImplementedError with a short message can improve UX.

Example:

 TORCH_LIBRARY_IMPL(trtllm, CUDA, m)
 {
     m.impl("fp4_quantize", TORCH_FN(torch_ext::fp4_quantize));
     m.impl("calculate_nvfp4_global_scale", TORCH_FN(torch_ext::calculate_nvfp4_global_scale));
 }
+
+TORCH_LIBRARY_IMPL(trtllm, CPU, m)
+{
+    m.impl("calculate_nvfp4_global_scale", [](at::Tensor const&, c10::optional<at::Tensor> const&) -> at::Tensor {
+        C10_THROW_ERROR(NotImplementedError, "calculate_nvfp4_global_scale is CUDA-only");
+    });
+}
cpp/tensorrt_llm/kernels/quantization.cu (1)

2-2: Update copyright year to 2025

The copyright header should reflect the current year (2025) for new code additions.

- * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2025, NVIDIA CORPORATION.  All rights reserved.
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📒 Files selected for processing (6)
  • cpp/tensorrt_llm/kernels/quantization.cu (3 hunks)
  • cpp/tensorrt_llm/kernels/quantization.h (1 hunks)
  • cpp/tensorrt_llm/thop/fp4Quantize.cpp (2 hunks)
  • cpp/tensorrt_llm/thop/fp4Quantize.h (1 hunks)
  • tensorrt_llm/_torch/modules/fused_moe/fused_moe_wide_ep.py (1 hunks)
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📚 Learning: 2025-07-28T17:06:08.621Z
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File: tests/integration/test_lists/qa/examples_test_list.txt:494-494
Timestamp: 2025-07-28T17:06:08.621Z
Learning: In TensorRT-LLM testing, it's common to have both CLI flow tests (test_cli_flow.py) and PyTorch API tests (test_llm_api_pytorch.py) for the same model. These serve different purposes: CLI flow tests validate the traditional command-line workflow, while PyTorch API tests validate the newer LLM API backend. Both are legitimate and should coexist.

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tests/unittest/_torch/thop/test_fp4_calculate_global_scale.py

99-99: Line too long (121 > 120)

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🔇 Additional comments (5)
cpp/tensorrt_llm/kernels/quantization.h (1)

91-94: computePerTokenGlobalScaleForFP4Quantization parameter names are consistent
The declaration in cpp/tensorrt_llm/kernels/quantization.h (line 92) and the definition in cpp/tensorrt_llm/kernels/quantization.cu (line 374) use the same parameter names and order (b, m, n, input, tokensPerBatch, globalScale, multiProcessorCount, stream). No changes needed.

cpp/tensorrt_llm/kernels/quantization.cu (4)

305-324: VecType implementation looks correct

The template specializations for half and __nv_bfloat16 properly map to their vectorized types (half2 and __nv_bfloat162), which is appropriate for vectorized max-abs reduction.


406-407: Consolidate duplicate template instantiations

The template instantiations for computePerTokenGlobalScaleForFP4Quantization appear to be duplicated - once for half (lines 406-407) and once for __nv_bfloat16 (lines 417-419). This is correct and matches the pattern for other functions in the file.

Also applies to: 417-419


343-344: Synchronization in blockReduceMaxV2 is correct

The blockReduceMaxV2 implementation internally handles thread coordination:

  • After each warp computes its partial maximum via warpReduceMaxV2, threads with lane == 0 write their results into the shared array.
  • A full-block barrier (__syncthreads()) follows, ensuring all writes complete before any thread reads from shared memory.
  • Finally, each thread loads either its warp’s shared result or a sentinel value and calls warpReduceMaxV2 again to compute the block-wide maximum.

No additional barriers are required, as warp‐level shuffles used by warpReduceMaxV2 are implicitly synchronous within a warp. You can safely call blockReduceMaxV2 without adding extra synchronization.


379-379: Quantization kernel alignment requirement needs clarification

The assertion

TLLM_CHECK(n % (ElemsPerVec * 32) == 0 and b > 0);

ensures that the number of elements per row (n) is a multiple of ElemsPerVec * 32 (i.e. vector-width × warp size), not just ElemsPerVec. As a result, for FP16 (ElemsPerVec = 8) you require n % 256 == 0, whereas the bare vectorized load only needs n % 8 == 0.

• If the extra factor of 32 is intentional (to guarantee full-warp coalesced loads for performance), please document this rationale in a comment above the check.
• Otherwise, consider relaxing the check to

TLLM_CHECK(n % ElemsPerVec == 0 and b > 0);

so that smaller, non-warp-aligned row sizes are supported.

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@yilin-void yilin-void requested a review from a team as a code owner August 22, 2025 01:43
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⚠️ Outside diff range comments (1)
tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py (1)

1-1: Add NVIDIA copyright header to cpp_custom_ops.py

This source file is missing the required NVIDIA copyright header mandated by CODING_GUIDELINES.md for all non-test Python files. Please prepend the following at the very top of tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py:

+# Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 from typing import List, Optional

• File to update:
tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py

• After inserting, verify the exact punctuation, capitalization, and any surrounding blank lines match the project’s canonical header style (you can mirror an existing header from another source file, e.g., a .cpp in the repo).

🧹 Nitpick comments (1)
tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py (1)

182-187: Add an optional default for tokens_per_batch in the meta stub and early‐error checks

You can safely make the second argument optional in the fake (meta) kernel without impacting the real CUDA dispatch or existing Python‐op signature. The C++ registration already declares

m.def("calculate_nvfp4_global_scale(Tensor input, Tensor? tokensPerBatch) -> Tensor");

so downstream calls (including all existing call sites and tests on CUDA) will continue to require you to pass a second argument when executing on CUDA. The Python‐only default (=None) and shape assertions live entirely in the fake kernel used during tracing/compile.

– Modify the fake registration in tensorrt_llm/_torch/custom_ops/cpp_custom_ops.py:

 @torch.library.register_fake("trtllm::calculate_nvfp4_global_scale")
-def _(input: torch.Tensor, tokens_per_batch: Optional[torch.Tensor]):
+def _(input: torch.Tensor, tokens_per_batch: Optional[torch.Tensor] = None):
     shape = list(input.shape)
     shape[-1] = 1
+    # Meta‐time sanity checks
+    if tokens_per_batch is not None:
+        assert tokens_per_batch.ndim == 1, "tokens_per_batch must be 1D [batch]"
+        assert tokens_per_batch.shape[0] == input.shape[0], \
+            "tokens_per_batch length must match input.batch size"
     return input.new_empty(shape, dtype=torch.float32)

– No changes are needed to any C++ files—the schema in
cpp/tensorrt_llm/thop/fp4Quantize.cpp already matches (Tensor, Tensor?) -> Tensor.
– All existing Python call sites (e.g. in fused_moe_wide_ep.py) still pass two arguments.
– The real‐device tests in
tests/unittest/_torch/thop/test_fp4_calculate_global_scale.py
will continue to run unchanged, since they invoke the CUDA kernel, not the fake.

This adds lightweight meta‐time validation and improves trace‐time ergonomics without affecting production behavior.

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Some nits. LGTM.

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PR_Github #16095 [ run ] completed with state SUCCESS
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@yilin-void yilin-void force-pushed the dev/fp4_global_scale branch from 8197039 to aecf242 Compare August 26, 2025 02:54
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PR_Github #16509 [ run ] triggered by Bot

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PR_Github #16509 [ run ] completed with state SUCCESS
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@yilin-void yilin-void merged commit 040f4c7 into NVIDIA:main Aug 26, 2025
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@yilin-void yilin-void deleted the dev/fp4_global_scale branch September 28, 2025 03:27
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