UefiCpuPkg: RiscV64: initialize FPU

The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <[email protected]>
NVIDIA · Oct 4, 2024 · f8c7385 · f8c7385
1 parent 28dd588
commit f8c7385
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diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -359,6 +359,12 @@ InitializeCpu (
   Status = RiscVConfigureMmu ();
   ASSERT_EFI_ERROR (Status);
 
+  //
+  // Initialize FPU
+  //
+  Status = RiscVInitializeFpu ();
+  ASSERT_EFI_ERROR (Status);
+
   //
   // Install Boot protocol
   //

diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -14,6 +14,7 @@
 
 #include <Protocol/Cpu.h>
 #include <Protocol/RiscVBootProtocol.h>
+#include <Library/BaseRiscVFpuLib.h>
 #include <Library/BaseRiscVSbiLib.h>
 #include <Library/BaseRiscVMmuLib.h>
 #include <Library/BaseLib.h>

diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
@@ -38,6 +38,7 @@
   PeCoffGetEntryPointLib
   RiscVSbiLib
   RiscVMmuLib
+  RiscVFpuLib
   CacheMaintenanceLib
 
 [Sources]

diff --git a/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h b/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h
@@ -0,0 +1,21 @@
+/** @file
+
+  Copyright (c) 2024, Canonical Services Ltd<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef BASE_RISCV_FPU_LIB_H_
+#define BASE_RISCV_FPU_LIB_H_
+
+/**
+  Initialize floating point unit
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVInitializeFpu (
+  VOID
+  );
+
+#endif /* BASE_RISCV_FPU_LIB_H_ */
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
@@ -0,0 +1,26 @@
+## @file
+#  RISC-V FPU library.
+#
+#  Copyright (c) 2024, Canonical Services Ltd
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION         = 0x0001001b
+  BASE_NAME           = BaseRiscVFpuLib
+  FILE_GUID           = e600fe4d-8595-40f3-90a0-5f043ce155c2
+  MODULE_TYPE         = BASE
+  VERSION_STRING      = 1.0
+  LIBRARY_CLASS       = RiscVFpuLib
+
+[Sources]
+  RiscVFpuCore.S
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S
@@ -0,0 +1,22 @@
+/** @file
+*
+*  Copyright (c) 2024, Canonical Services Ltd
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/BaseRiscVFpuLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+//
+// Initialize floating point unit
+//
+ASM_FUNC (RiscVInitializeFpu)
+  csrr  a0, CSR_SSTATUS
+  li    a1, MSTATUS_FS
+  or    a0, a0, a1
+  csrw  CSR_SSTATUS, a0
+  csrw  CSR_FCSR, x0
+  li    a0, 0
+  ret
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
@@ -75,6 +75,8 @@
   SmmRelocationLib|Include/Library/SmmRelocationLib.h
 
 [LibraryClasses.RISCV64]
+  ##  @libraryclass  Provides function to initialize the FPU.
+  RiscVFpuLib|Include/Library/BaseRiscVFpuLib.h
   ##  @libraryclass  Provides functions to manage MMU features on RISCV64 CPUs.
   ##
   RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -224,6 +224,7 @@
 [Components.RISCV64]
   UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
   UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
   UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
   UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
   UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf