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design: working on memory sub #24

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design: working on memory sub #24

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69 changes: 65 additions & 4 deletions rtl/ahb/devices/SubMemCtrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,71 @@
@note See https://github.com/NYU-Processor-Design/nyu-mem
*/

module SubMemCtrl(
AHBCommon_if.subordinate sub,
MemCommon_if.memCtrl mem
/**
@brief Subordinate to interface witht he memory controller

@note See https://github.com/NYU-Processor-Design/nyu-mem
*/

module SubMemCtrl #(
parameter ADDR_WIDTH = 32, // Address width
parameter DATA_WIDTH = 32 // Data width
)(
input wire HCLK, // clock
input wire HRESETn, // reset
input wire [ADDR_WIDTH-1:0] HADDR, // address
input wire HWRITE, // write
input wire [1:0] HTRANS, // transfer
input wire [2:0] HSIZE, // tranfer size
input wire [DATA_WIDTH-1:0] HWDATA, // write data
output wire [DATA_WIDTH-1:0] HRDATA, // read data
output wire HREADY, // transfer ready
output wire [1:0] HRESP, // transfer response
// Memory Controller Interface
output wire [ADDR_WIDTH-1:0] MemAddr, // Memory address
output wire MemWrite, // Memory write enable
output wire [DATA_WIDTH-1:0] MemWData, // Memory write data
input wire [DATA_WIDTH-1:0] MemRData, // Memory read data
output wire MemReq, // Memory request signal
input wire MemReady // Memory ready signal
Comment on lines +14 to +33
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All of this has been defined in the two interfaces, AHBCommon_if and MemCommon_if. You can see SubDummy.sv to review usage.

We want them in an interface so other teams know how to interface with our code. For example, the memory team can use MemCommon_if as a blueprint to make their modules.

To get started, define your module as follows

module SubMemCtrl(
  AHBCommon_if.subordinate sub,
  MemCommon_if.memCtrl mem
);

endmodule

);
// General subordinate logic follows

reg [DATA_WIDTH-1:0] internalRData;
reg internalReady;
reg [1:0] internalResp;
Comment on lines +36 to +38
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I don't understand why these should be "internal" to the controller subordinate.


assign HRDATA = internalRData;
assign HREADY = internalReady;
assign HRESP = internalResp;
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Response statuses are in an enum (ahb_resp_t) defined in AHBCommon_pkg.


assign MemAddr = HADDR;
assign MemWrite = HWRITE && (HTRANS[1] && HREADY); // init write
assign MemWData = HWDATA;
assign MemReq = HTRANS[1] && HREADY; // Transfer request signal

// AHB to Memory Controller Interface Logic
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
internalRData <= 0;
internalReady <= 0;
internalResp <= 2'b00; // OKAY
end else begin
internalReady <= MemReady;
if (MemReady) begin
if (HWRITE) begin
// handle write
internalResp <= 2'b00; // OKAY
end else begin
// handle read
internalRData <= MemRData;
internalResp <= 2'b00; // OKAY
end
end else begin
internalResp <= 2'b01; // WAIT state
end
end
end

endmodule


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