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rtl/wbp_mux: fix de-assertion of address
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Original file line number | Diff line number | Diff line change |
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@@ -3,14 +3,16 @@ | |
-- | ||
-- Authors: Niklaus Leuenberger <[email protected]> | ||
-- | ||
-- Version: 0.1 | ||
-- Version: 0.2 | ||
-- | ||
-- Entity: wbp_mux_tb | ||
-- | ||
-- Description: Testbench for the one to many interconnect. | ||
-- | ||
-- Changes: 0.1, 2024-08-25, leuen4 | ||
-- initial version | ||
-- 0.2, 2024-10-08, leuen4 | ||
-- fix too early de-assertion of address | ||
-- ============================================================================= | ||
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LIBRARY ieee; | ||
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@@ -97,10 +99,7 @@ BEGIN | |
WAIT UNTIL rising_edge(clk) AND master_miso.stall = '0' FOR MAX_DELAY; | ||
assert master_miso.stall = '0' report "slave did not deassert stall" severity failure; | ||
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master_mosi.adr <= (others => '0'); | ||
master_mosi.dat <= (others => '0'); | ||
master_mosi.we <= '0'; | ||
master_mosi.sel <= (others => '0'); | ||
master_mosi.stb <= '0'; | ||
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for i in 1 to MAX_DELAY / CLK_PERIOD loop | ||
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@@ -114,6 +113,9 @@ BEGIN | |
ASSERT master_miso.dat = data report "read data invalid" severity failure; | ||
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master_mosi.cyc <= '0'; | ||
master_mosi.adr <= (others => '0'); | ||
master_mosi.we <= '0'; | ||
master_mosi.sel <= (others => '0'); | ||
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WAIT UNTIL rising_edge(clk); | ||
end procedure sim_read; | ||
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@@ -135,10 +137,7 @@ BEGIN | |
WAIT UNTIL rising_edge(clk) AND master_miso.stall = '0' FOR MAX_DELAY; | ||
assert master_miso.stall = '0' report "slave did not deassert stall" severity failure; | ||
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master_mosi.adr <= (others => '0'); | ||
master_mosi.dat <= (others => '0'); | ||
master_mosi.we <= '0'; | ||
master_mosi.sel <= (others => '0'); | ||
master_mosi.stb <= '0'; | ||
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for i in 1 to MAX_DELAY / CLK_PERIOD loop | ||
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@@ -150,6 +149,9 @@ BEGIN | |
assert master_miso.err = '1' report "slave did NOT respond with err" severity failure; | ||
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master_mosi.cyc <= '0'; | ||
master_mosi.adr <= (others => '0'); | ||
master_mosi.we <= '0'; | ||
master_mosi.sel <= (others => '0'); | ||
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WAIT UNTIL rising_edge(clk); | ||
end procedure sim_read_err; | ||
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