Bootblock 0.5.4

    https://github.com/Nuvoton-Israel/npcm8xx-bootblock/releases/tag/A35_BootBlock_0.5.4
       * Add two new header fields:
         - pll0_override: can be used to set pll0, unless CPU != MC frequency. In this case override would fail.
         - i3c divider. once it's set P.eCI root complex will not function anymore. Recommendation for I3C users: set CPU = MC = 1000, pll0_override = 625, i3c_div = 13. For RC users: pll0_override = 0, i3c_div = 0xFF.
       * Add MC support for 300MHz.
       * Add CPU support for 325MHz, 625MHz.

signed-off-by:[email protected]

Sources/Arbel_A35_BootBlock_RelLetter.txt

@@ -7,8 +7,8 @@
 ----------------------------------------------------------------------
 
 # NPCM8XX bootBlock Package Release Letter
-Version: 00.05.03
-Date:    Sep 2024
+Version: 00.05.04
+Date:    Dec 2024
 
 
 # PACKAGE CONTENTS
@@ -56,6 +56,18 @@ to flash via the IGPS (https://github.com/Nuvoton-Israel/igps) or other means.
 
 # ENHANCEMENTS
 ----------------
+version 0.5.4     - Dec 10th 2024
+============
+- Add two new header fields:
+  - pll0_override: can be used to set pll0, unless CPU != MC frequency. In this case override would fail.
+  - i3c divider. once it's set PCI root complex will not function anymore.
+  Recommendation for I3C users: set CPU = MC = 1000, pll0_override = 625, i3c_div = 13.
+  For RC users: pll0_override = 0, i3c_div = 0xFF.
+- Add MC support for 300MHz.
+- Add CPU support for 325MHz, 625MHz.
+
+# HISTORY
+---------------
 version 0.5.3     - Nov 11th 2024
 ============
 - Fix MC trim override options.
@@ -66,8 +78,6 @@ version 0.5.3     - Nov 11th 2024
 - Add an option stack profiler (compilation flag).
 - Add an optional compilation flag for SORT. If it's set then fail boot if sweep fails (eye_size smaller then 12) 
 
-# HISTORY
----------------
 version 0.5.2     - Sep 15th 2024
 ============
 - Bug fix: Errata fix: 1.7 eSPI FATAL_ERROR: Set ESPI_ESPI_ENG to 0x40 (remove RMW to set bit 6).

Sources/SWC_HAL/ModuleDrivers/clk/4/clk_drv.c

@@ -42,9 +42,11 @@
 /* PLLCON0 and PLLCON2 possible values:                                                                    */
 /*---------------------------------------------------------------------------------------------------------*/
 #define CLK_125MHZ_PLLCON0_2_REG_CFG    0x00284401
+#define CLK_325MHZ_PLLCON0_2_REG_CFG    0x003C2401
 #define CLK_333MHZ_PLLCON0_2_REG_CFG    0x00A02403
 #define CLK_500MHZ_PLLCON0_2_REG_CFG    0x00282201
 #define CLK_600MHZ_PLLCON0_2_REG_CFG    0x00302201
+#define CLK_625MHZ_PLLCON0_2_REG_CFG    0x00322201
 #define CLK_666MHZ_PLLCON0_2_REG_CFG    0x00A02203
 #define CLK_700MHZ_PLLCON0_2_REG_CFG    0x001C2101
 #define CLK_720MHZ_PLLCON0_2_REG_CFG    0x00902105
@@ -827,23 +829,21 @@ void CLK_ConfigureEMCClock (UINT32 ethNum)
 void CLK_ConfigureGMACClock (UINT32 ethNum)
 {
     UINT32 source = 0;
-	UINT32 div = 0;
-    UINT32 sel =  READ_REG_FIELD(CLKSEL, CLKSEL_RGSEL);
+    UINT32 div = 0;
 
-    switch (sel)
+    source = CLK_GetPll0Freq();
+
+    // use pll0 if it's a 125 multiplication. If it's set to something else - use pll1 and try to get to 125MHz
+    if ((source % (125 * _1MHz_)) == 0)
+    {
+        SET_REG_FIELD (CLKSEL, CLKSEL_RGSEL, CLKSEL_RGSEL_PLL0);
+    }
+    else
     {
-    case CLKSEL_RGSEL_PLL0:
-        source = CLK_GetPll0Freq();
-        break;
-    case CLKSEL_RGSEL_PLL1:
         source = CLK_GetPll1Freq();
-        break;
-    case CLKSEL_RGSEL_CLKREF:
-        source = EXT_CLOCK_FREQUENCY_HZ;
-        break;
-    default:
-        ASSERT(0);
+        SET_REG_FIELD (CLKSEL, CLKSEL_RGSEL, CLKSEL_RGSEL_PLL1);
     }
+
     div = source / (125 * _1MHz_); // GMAC should be 125MHz always.
 
     SET_REG_FIELD(CLKDIV4, CLKDIV4_RGREFDIV, CLKDIV4_RGREFDIV_DIV(div)); 
@@ -866,13 +866,13 @@ void CLK_ConfigureRootComplexClock (void)
 
     switch (sel)
     {
-    case CLKSEL_RGSEL_PLL0:
+    case CLKSEL_RCPCKSEL_PLL0:
         source = CLK_GetPll0Freq();
         break;
-    case CLKSEL_RGSEL_PLL1:
+    case CLKSEL_RCPCKSEL_PLL1:
         source = CLK_GetPll1Freq();
         break;
-    case CLKSEL_RGSEL_CLKREF:
+    case CLKSEL_RCPCKSEL_CLKREF:
         source = EXT_CLOCK_FREQUENCY_HZ;
         break;
     default:
@@ -883,6 +883,20 @@ void CLK_ConfigureRootComplexClock (void)
     SET_REG_FIELD(CLKDIV4, CLKDIV4_RCPREFDIV, CLKDIV4_RCPREFDIV_DIV(div)); 
 }
 
+/*---------------------------------------------------------------------------------------------------------*/
+/* Function:        CLK_Configure_I3C_Clock                                                                */
+/*                                                                                                         */
+/* Parameters:      div - value to divide the clock. Can be 1..16                                          */
+/* Returns:         none                                                                                   */
+/* Side effects:                                                                                           */
+/* Description:                                                                                            */
+/*                  This routine configures I3C clocks                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+void CLK_Configure_I3C_Clock (UINT8 div)
+{
+    div = MIN(div, 16);
+    SET_REG_FIELD(CLKDIV4, CLKDIV4_RCPREFDIV, CLKDIV4_RCPREFDIV_DIV(div)); 
+}
 
 /*---------------------------------------------------------------------------------------------------------*/
 /* Function:        CLK_ConfigureSDClock                                                                   */
@@ -1999,7 +2013,8 @@ DEFS_STATUS CLK_Configure_CPU_MC_Clock (UINT32 mcFreq, UINT32 cpuFreq, UINT32 pl
     /*---------------------------------------------------------------------------------------------------------*/
     /* PLLCON 1 possible values (notice that PLL1 has a divider /2, so OTDV1 is smaller in half                */
     /*---------------------------------------------------------------------------------------------------------*/
-    if ( mcFreq <= 500000000)      pllcon1_L = CLK_500MHZ_PLLCON1_REG_CFG       ;
+    if      ( mcFreq <= 300000000)      pllcon1_L = CLK_300MHZ_PLLCON1_REG_CFG       ;
+	else if ( mcFreq <= 500000000)      pllcon1_L = CLK_500MHZ_PLLCON1_REG_CFG       ;
     else if ( mcFreq <= 666000000)      pllcon1_L = CLK_666MHZ_PLLCON1_REG_CFG       ;
     else if ( mcFreq <= 700000000)      pllcon1_L = CLK_700MHZ_PLLCON1_REG_CFG       ;
     else if ( mcFreq <= 720000000)      pllcon1_L = CLK_720MHZ_PLLCON1_REG_CFG       ;
@@ -2025,9 +2040,11 @@ DEFS_STATUS CLK_Configure_CPU_MC_Clock (UINT32 mcFreq, UINT32 cpuFreq, UINT32 pl
     /* PLLCON 0 possible values (notice that PLL1 in Z2 has a divider /2, so OTDV1 is smaller in half      */
     /*---------------------------------------------------------------------------------------------------------*/
     if ( pll0_freq_tmp <= 125000000 )  pllcon0_L = CLK_125MHZ_PLLCON0_2_REG_CFG ;
+	else if ( pll0_freq_tmp <= 325000000 )  pllcon0_L = CLK_325MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 333000000 )  pllcon0_L = CLK_333MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 500000000 )  pllcon0_L = CLK_500MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 600000000 )  pllcon0_L = CLK_600MHZ_PLLCON0_2_REG_CFG ;
+	else if ( pll0_freq_tmp <= 625000000 )  pllcon0_L = CLK_625MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 666000000 )  pllcon0_L = CLK_666MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 700000000 )  pllcon0_L = CLK_700MHZ_PLLCON0_2_REG_CFG ;
     else if ( pll0_freq_tmp <= 720000000 )  pllcon0_L = CLK_720MHZ_PLLCON0_2_REG_CFG ;
@@ -2078,9 +2095,9 @@ DEFS_STATUS CLK_Configure_CPU_MC_Clock (UINT32 mcFreq, UINT32 cpuFreq, UINT32 pl
 
     /*-----------------------------------------------------------------------------------------------------*/
     /* PLL0 handling : Check if PLL is set to the value CPU is set: Notice:even if MC freq == CPU freq,    */
-    /* both will be connected to PLL1, and PLL0 will be turned off.                                        */
+    /* both will be connected to PLL1, and PLL0 will be turned off, unless pll0_override is set            */
     /*-----------------------------------------------------------------------------------------------------*/
-    if (pllcon0_L != (REG_READ(PLLCON0) & 0x7FFFFFFF) && (mcFreq != cpuFreq))
+    if (pllcon0_L != (REG_READ(PLLCON0) & 0x7FFFFFFF) && ((mcFreq != cpuFreq) || (pll0_freq != 0)))
     {
         clksel_now_l = REG_READ(CLKSEL);
 

Sources/SWC_HAL/ModuleDrivers/clk/clk_if.h

@@ -184,6 +184,17 @@ void CLK_ConfigureGMACClock (UINT32 ethNum);
 /*---------------------------------------------------------------------------------------------------------*/
 void CLK_ConfigureRootComplexClock (void);
 
+/*---------------------------------------------------------------------------------------------------------*/
+/* Function:        CLK_Configure_I3C_Clock                                                                */
+/*                                                                                                         */
+/* Parameters:      div - value to divide the clock. Can be 1..16                                          */
+/* Returns:         none                                                                                   */
+/* Side effects:                                                                                           */
+/* Description:                                                                                            */
+/*                  This routine configures I3C clocks                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+void CLK_Configure_I3C_Clock (UINT8 div);
+
 /*---------------------------------------------------------------------------------------------------------*/
 /* Function:        CLK_ConfigureSDClock                                                                   */
 /*                                                                                                         */

Sources/SWC_HAL/version.h

@@ -16,7 +16,7 @@
 
 #define SWC_HAL_MAJOR   4
 #define SWC_HAL_MINOR   0
-#define SWC_HAL_REV     5
+#define SWC_HAL_REV     6
 #define SWC_HAL_PATCH   0
 
 #define SWC_HAL_VERSION         MAKE32(MAKE16(SWC_HAL_PATCH, SWC_HAL_REV), MAKE16(SWC_HAL_MINOR, SWC_HAL_MAJOR))

Sources/source/boot.h

@@ -94,7 +94,7 @@ typedef union BOOTBLOCK_HEADER_tag
 		UINT8   startTag[8];                   // 0            8           AA55_0850h, 424F_4F54h (‘BOOT’)
 		UINT8   signature[96];                 // 8            256         Boot Block ECC signature decrypted with Customer’s Private Key
 
-		UINT8   reserved[152];                 // 0x68         152         Reserved for future use, not signed
+		UINT8   reserved[152];                 // 0x68         152         Reserved for future use, signed.
 		//  Start signed area:
 		UINT32  version;                       // 0x100       4           Version (Major.Minor)
 		UINT32  vendor;                        // 0x104       4
@@ -113,7 +113,7 @@ typedef union BOOTBLOCK_HEADER_tag
 		UINT32  NoECC_Region_0_End;            // 0x124       4
 		UINT32  NoECC_Region_1_Start;          // 0x128       4
 		UINT32  NoECC_Region_1_End;            // 0x12C       4
-		UINT32  dram_max_size;                 // 0x130       4             added in version 0.0.6.
+		UINT32  dram_max_size;                 // 0x130       4
 		UINT8   mc_config;                     // 0x134       1
 		UINT8   host_if;                       // 0x135       1
 
@@ -145,7 +145,7 @@ typedef union BOOTBLOCK_HEADER_tag
 		UINT8   fiu1_divider;                   // 0x150       1
 		UINT8   fiu3_divider;                   // 0x151       1
 		UINT8   gmmap;                          // 0x152       1
-		UINT8   reservedSigned2;                // 0x153       1
+		UINT8   i3c_rc_divider;                 // 0x153       1
 		UINT32  baud;                           // 0x154       4
 
 		UINT32  fiu_cfg_drd_set[3];             // 0x158       4 * 3
@@ -166,8 +166,9 @@ typedef union BOOTBLOCK_HEADER_tag
 		UINT32  NoECC_Region_6_End;            // 0x18C       4
 		UINT32  NoECC_Region_7_Start;          // 0x190       4
 		UINT32  NoECC_Region_7_End;            // 0x194       4
+		UINT32  pll0_override;                 // 0x198       4
 
-		UINT8   reservedSigned3[0x60];         // 0x198       0x60        Reserved for future use, signed.
+		UINT8   reservedSigned3[0x5C];         // 0x202       0x5C        Reserved for future use, signed.
 
  		UINT32  destAddr;                      // 0x1F8
  		UINT32  codeSize;                      // 0x1FC
@@ -245,6 +246,8 @@ UINT32          BOOTBLOCK_Get_CPU_freq (void);
 void            BOOTBLOCK_Get_DDR_Setup (DDR_Setup *ddr_setup);
 HOST_IF_T       BOOTBLOCK_Get_host_if (void);
 UINT8           BOOTBLOCK_Get_SPI_clk_divider (UINT spi);
+UINT8           BOOTBLOCK_Get_i3c_RC_clk_divider (void);
+UINT32          BOOTBLOCK_Get_pll0_override (void);
 UART_BAUDRATE_T BOOTBLOCK_GetUartBaud (void);
 UINT32          BOOTBLOCK_Get_FIU_DRD_CFG (UINT32 fiu);
 

Sources/source/bootblock_boot.c

@@ -321,6 +321,46 @@ UINT8   BOOTBLOCK_Get_SPI_clk_divider (UINT spi)
 	return val_header;
 }
 
+/*---------------------------------------------------------------------------------------------------------*/
+/* Function:        BOOTBLOCK_Get_i3c_RC_clk_divider                                                       */
+/*                                                                                                         */
+/* Parameters:                                                                                             */
+/*                                                                                                         */
+/* Returns:        get I3C and RC divder (shared) clk divider from header.                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+UINT8   BOOTBLOCK_Get_i3c_RC_clk_divider (void)
+{
+	UINT8 val_header = 0;
+
+	BOOTBLOCK_HEADER_T *bootBlockHeader = (BOOTBLOCK_HEADER_T*)BOOTBLOCK_HEADER_ADDR;
+
+	val_header = bootBlockHeader->header.i3c_rc_divider;
+
+	return val_header;
+}
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Function:        BOOTBLOCK_Get_pll0_override                                                            */
+/*                                                                                                         */
+/* Parameters:                                                                                             */
+/*                                                                                                         */
+/* Returns:        override PLL0. This is only possible if MC==CPU freq.                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+UINT32   BOOTBLOCK_Get_pll0_override (void)
+{
+	UINT32 val_header = 0;
+
+	BOOTBLOCK_HEADER_T *bootBlockHeader = (BOOTBLOCK_HEADER_T*)BOOTBLOCK_HEADER_ADDR;
+
+	val_header = bootBlockHeader->header.pll0_override;
+
+	if (val_header == 0xFFFFFFFF)
+	{
+		val_header = 0;
+	}
+
+	return val_header;
+}
 
 #undef BOOT_C
 

Sources/source/bootblock_main.c

@@ -307,6 +307,7 @@ static void bootblock_ChangeClocks (DDR_Setup *ddr_setup)
 	DEFS_STATUS status;
 	UINT32 straps = 0;
 	UINT32 clk4Freq;
+	UINT32 pll0_override = 0;
 	UINT8 div_50MHz;
 	UINT8 div;
 	volatile UINT cntfrq_val;
@@ -365,7 +366,19 @@ static void bootblock_ChangeClocks (DDR_Setup *ddr_setup)
 			serial_printf("Change freq cpu %d mc %d\n", cpuFreq, mcFreq);
 			cpuFreq = cpuFreq * 1000000;
 			mcFreq = mcFreq * 1000000;
-			status = CLK_Configure_CPU_MC_Clock(mcFreq, cpuFreq, 0);
+
+			// if MC==CPU frequency, can change pll0 to other values according to header value:
+			if (cpuFreq == mcFreq)
+			{
+				pll0_override = BOOTBLOCK_Get_pll0_override();
+				if (pll0_override != 0)
+				{
+					serial_printf (KMAG "Override PLL0 to %d\n" KNRM, pll0_override);
+				}
+				pll0_override = pll0_override * 1000000;
+			}
+
+			status = CLK_Configure_CPU_MC_Clock(mcFreq, cpuFreq, pll0_override);
 			if ((status != DEFS_STATUS_OK) && (status != DEFS_STATUS_SYSTEM_NOT_INITIALIZED))
 			{
 				serial_printf("can't set plls, stat = %d\n", status);
@@ -384,9 +397,22 @@ static void bootblock_ChangeClocks (DDR_Setup *ddr_setup)
 		SET_REG_FIELD(AHBCKFI, AHBCKFI_AHB_CLK_FRQ, CLK_GetCPFreq() / _1MHz_);
 		serial_printf_init();
 
+		BOOTBLOCK_Get_pll0_override ();
+
 		CLK_ConfigureGMACClock(0);
-		CLK_ConfigureRootComplexClock();
 		CLK_SetPixelClock();
+
+		// override i3c\RC divider from header:
+		div = BOOTBLOCK_Get_i3c_RC_clk_divider();
+		if ((div != 0) && (div != 0xFF))
+		{
+			serial_printf ("Override i3c and RC clk div %d\nWarning: RC not supported anymore\n", div);
+			CLK_Configure_I3C_Clock (div);
+		}
+		else
+		{
+			CLK_ConfigureRootComplexClock();
+		}
 	}
 
 	//  Update FIU dividers:
@@ -512,7 +538,7 @@ static void bootblock_PrintClocks (void)
 	}
 
 	if (CLK_Get_RC_Phy_and_I3C_Clock() != 100000000) {
-		serial_printf(KRED "ERROR RC value not 100MHz\n" KNRM);
+		serial_printf(KMAG "warning RC value not 100MHz, PCI root complex not supported\n" KNRM);
 	}
 
 	return;

Sources/source/bootblock_version.c

@@ -43,7 +43,7 @@ const BOOTBLOCK_Version_T bb_version = {
 
     #define BOOT_DEBUG_VAL 0x00000000
 
-	.BootblockVersion = (BOOT_DEBUG_VAL | 0x000503)     //ver 00.05.03
+	.BootblockVersion = (BOOT_DEBUG_VAL | 0x000504)     //ver 00.05.04
 };
 
 #undef BOOTBLOCK_VERSION_C

crc_no_tip.log

@@ -1 +1 @@
-0x9E0EAA11
+0x3770E150

crc_tip.log

@@ -1 +1 @@
-0xAF4067A6
+0x041897A9