CSR: make mstatus.fs writable for software FPU emulation (#196)

FS must not be read-only zero to allow software emulation of FPU.
OSCPU · May 15, 2024 · 3630ab5 · 3630ab5
1 parent 99214de
commit 3630ab5
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diff --git a/ready-to-run/riscv64-nemu-interpreter-so b/ready-to-run/riscv64-nemu-interpreter-so
diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala
@@ -306,7 +306,6 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     GenMask(35, 32)  | // SXL and UXL cannot be changed
     GenMask(31, 23)  | // WPRI
     GenMask(16, 15)  | // XS is read-only
-    GenMask(14, 13)  | // FS is read-only
     GenMask(6)       | // UBE, always little-endian (0)
     GenMask(4)       | // WPRI
     GenMask(2)       | // WPRI
@@ -338,7 +337,8 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   // val sstatus = RegInit(UInt(XLEN.W), "h00000000".U)
   val sstatusWmask = (~ZeroExt((
     GenMask(63, 20)  | // SD, WPRI, UXL, WPRI
-    GenMask(17, 9)   | // WPRI, XS, FS, WPRI, VS
+    GenMask(17, 15)  | // WPRI, XS
+    GenMask(12, 9)   | // WPRI, VS
     GenMask(7, 6)    | // WPRI, UBE
     GenMask(4, 2)    | // WPRI
     GenMask(0)         // WPRI