Replace assert and fatal for all generated RTLs

Makefile

@@ -61,8 +61,10 @@ verilog: $(TOP_V)
 $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
 	mill -i generator.test.runMain $(SIMTOP) $(MILL_ARGS)
-	@sed -i 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
-	@sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V)
+	@for file in $(RTL_DIR)/*.$(RTL_SUFFIX); do                               \
+		sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' "$$file";           \
+		sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" "$$file";    \
+        done
 
 sim-verilog: $(SIM_TOP_V)