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Fix epc[0] is always 0, rather than being cleared only at the time of use. #150

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Fix epc[0] is always 0, rather than being cleared only at the time of use. #150

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66120cd
Fix:epc[0] value is always 0
Dec 6, 2023
30fa1ca
Fix:epc[0] value is always 0
Dec 6, 2023
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20 changes: 14 additions & 6 deletions src/main/scala/nutcore/backend/fu/CSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -385,7 +385,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{

// User Trap Handling
// MaskedRegMap(Uscratch, uscratch),
// MaskedRegMap(Uepc, uepc),
//Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
//MaskedRegMap(Uepc, uepc, wfn = (value: UInt) => (value & ~1.U(64.W))),

// MaskedRegMap(Ucause, ucause),
// MaskedRegMap(Utval, utval),
// MaskedRegMap(Uip, uip),
Expand All @@ -411,7 +413,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{

// Supervisor Trap Handling
MaskedRegMap(Sscratch, sscratch),
MaskedRegMap(Sepc, sepc),
//Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
MaskedRegMap(Sepc, sepc, wfn = (value: UInt) => (value & ~1.U(64.W))),

MaskedRegMap(Scause, scause),
MaskedRegMap(Stval, stval),
MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
Expand All @@ -437,7 +441,10 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{

// Machine Trap Handling
MaskedRegMap(Mscratch, mscratch),
MaskedRegMap(Mepc, mepc),
//MaskedRegMap(Mepc, mepc),
//Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
MaskedRegMap(Mepc, mepc, wfn = (value: UInt) => (value & ~1.U(64.W))),

MaskedRegMap(Mcause, mcause),
MaskedRegMap(Mtval, mtval),
MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable),
Expand Down Expand Up @@ -668,7 +675,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
mstatusNew.mpp := ModeU
mstatus := mstatusNew.asUInt
lr := false.B
retTarget := mepc(VAddrBits-1, 0)
retTarget := mepc
}

when (valid && isSret) {
Expand All @@ -681,7 +688,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
mstatusNew.spp := ModeU
mstatus := mstatusNew.asUInt
lr := false.B
retTarget := sepc(VAddrBits-1, 0)
retTarget := sepc
}

when (valid && isUret) {
Expand All @@ -692,7 +699,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
priviledgeMode := ModeU
mstatusNew.pie.u := true.B
mstatus := mstatusNew.asUInt
retTarget := uepc(VAddrBits-1, 0)
retTarget := uepc
}

when (raiseExceptionIntr) {
Expand Down Expand Up @@ -946,3 +953,4 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
}
}
}