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Bump DiffTest, Chisel 6.2.0 and Mill 0.11.7 #183

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merged 2 commits into from
Mar 9, 2024
Merged

Bump DiffTest, Chisel 6.2.0 and Mill 0.11.7 #183

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2c6b108
Support Difftest Argparser
klin02 Mar 6, 2024
eb99142
Bump Chisel 6.2.0 and Mill 0.11.7
poemonsense Mar 9, 2024
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2 changes: 1 addition & 1 deletion .mill-version
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Original file line number Diff line number Diff line change
@@ -1 +1 @@
0.11.6
0.11.7
13 changes: 7 additions & 6 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -21,23 +21,24 @@ DATAWIDTH ?= 64
BOARD ?= sim # sim pynq axu3cg
CORE ?= inorder # inorder ooo embedded

MILL_ARGS = -td $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
MILL_ARGS_ALL = $(MILL_ARGS)
MILL_ARGS_ALL += --target-dir $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
FPGA_ARGS =

ifneq ($(FIRTOOL),)
MILL_ARGS += --firtool-binary-path $(FIRTOOL)
MILL_ARGS_ALL += --firtool-binary-path $(FIRTOOL)
endif

MILL_ARGS += --split-verilog
MILL_ARGS_ALL += --split-verilog

.DEFAULT_GOAL = verilog

help:
mill -i generator.test.runMain top.$(TOP) --help $(MILL_ARGS)
mill -i generator.test.runMain top.$(TOP) --help $(MILL_ARGS_ALL)

$(TOP_V): $(SCALA_FILE)
mkdir -p $(@D)
mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS) $(FPGA_ARGS)
mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS_ALL) $(FPGA_ARGS)
@mv $(SIM_TOP_V) $(TOP_V)
sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
@git log -n 1 >> .__head__
Expand All @@ -60,7 +61,7 @@ verilog: $(TOP_V)

$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
mkdir -p $(@D)
mill -i generator.test.runMain $(SIMTOP) $(MILL_ARGS)
mill -i generator.test.runMain $(SIMTOP) $(MILL_ARGS_ALL)
@for file in $(RTL_DIR)/*.$(RTL_SUFFIX); do \
sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' "$$file"; \
sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" "$$file"; \
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4 changes: 2 additions & 2 deletions build.sc
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ import coursier.maven.MavenRepository

object ivys {
val scala = "2.13.12"
val chisel = ivy"org.chipsalliance::chisel:6.1.0"
val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.1.0"
val chisel = ivy"org.chipsalliance::chisel:6.2.0"
val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.2.0"
}

trait CommonModule extends ScalaModule {
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2 changes: 1 addition & 1 deletion difftest
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Submodule difftest updated 79 files
+23 −0 .clang-format
+38 −0 .github/workflows/format.yml
+114 −44 .github/workflows/main.yml
+1 −2 .mill-version
+48 −0 .scalafmt.conf
+21 −5 Makefile
+11 −4 README.md
+1 −1 build.sc
+5 −0 config/config.h
+17 −14 palladium.mk
+1 −1 scripts/coverage/statistics.py
+4 −0 scripts/palladium/argConfigs.qel
+2 −0 scripts/palladium/clock_gen.xel
+19 −0 scripts/palladium/compilerOptions.qel
+6 −0 scripts/palladium/run.tcl
+11 −0 scripts/palladium/run_debug.tcl
+158 −0 src/main/scala/Batch.scala
+49 −8 src/main/scala/Bundles.scala
+286 −100 src/main/scala/DPIC.scala
+93 −88 src/main/scala/Difftest.scala
+208 −149 src/main/scala/Gateway.scala
+105 −93 src/main/scala/Squash.scala
+78 −76 src/main/scala/common/Flash.scala
+6 −5 src/main/scala/common/LogPerfControl.scala
+80 −73 src/main/scala/common/Mem.scala
+4 −2 src/main/scala/common/SDCard.scala
+9 −11 src/main/scala/common/WiringControl.scala
+14 −14 src/test/csrc/common/SimJTAG.cpp
+4 −5 src/test/csrc/common/common.cpp
+22 −22 src/test/csrc/common/common.h
+138 −14 src/test/csrc/common/compress.cpp
+11 −5 src/test/csrc/common/compress.h
+9 −8 src/test/csrc/common/coverage.cpp
+101 −92 src/test/csrc/common/coverage.h
+9 −10 src/test/csrc/common/device.cpp
+13 −14 src/test/csrc/common/dut.h
+23 −14 src/test/csrc/common/flash.cpp
+44 −23 src/test/csrc/common/golden.cpp
+14 −14 src/test/csrc/common/golden.h
+26 −22 src/test/csrc/common/keyboard.cpp
+16 −15 src/test/csrc/common/lightsss.cpp
+10 −10 src/test/csrc/common/lightsss.h
+5 −5 src/test/csrc/common/macro.h
+1 −2 src/test/csrc/common/main.cpp
+52 −0 src/test/csrc/common/perf.cpp
+46 −0 src/test/csrc/common/perf.h
+75 −60 src/test/csrc/common/ram.cpp
+34 −24 src/test/csrc/common/ram.h
+46 −71 src/test/csrc/common/remote_bitbang.cpp
+12 −14 src/test/csrc/common/remote_bitbang.h
+12 −2 src/test/csrc/common/sdcard.cpp
+18 −16 src/test/csrc/common/uart.cpp
+15 −5 src/test/csrc/common/vga.cpp
+233 −160 src/test/csrc/difftest/difftest.cpp
+68 −49 src/test/csrc/difftest/difftest.h
+3 −7 src/test/csrc/difftest/difftrace.cpp
+69 −31 src/test/csrc/difftest/goldenmem.cpp
+11 −6 src/test/csrc/difftest/goldenmem.h
+47 −43 src/test/csrc/difftest/refproxy.cpp
+52 −18 src/test/csrc/difftest/refproxy.h
+21 −30 src/test/csrc/plugin/runahead/memdep.cpp
+18 −17 src/test/csrc/plugin/runahead/memdep.h
+85 −121 src/test/csrc/plugin/runahead/runahead.cpp
+28 −26 src/test/csrc/plugin/runahead/runahead.h
+18 −26 src/test/csrc/plugin/spikedasm/spikedasm.cpp
+2 −2 src/test/csrc/plugin/spikedasm/spikedasm.h
+125 −36 src/test/csrc/vcs/vcs_main.cpp
+112 −126 src/test/csrc/verilator/emu.cpp
+25 −17 src/test/csrc/verilator/emu.h
+44 −39 src/test/csrc/verilator/snapshot.cpp
+15 −11 src/test/csrc/verilator/snapshot.h
+1 −3 src/test/scala/DifftestMain.scala
+2 −2 src/test/vsrc/common/SimJTAG.v
+2 −0 src/test/vsrc/common/assert.v
+8 −0 src/test/vsrc/common/ref.v
+20 −10 src/test/vsrc/vcs/DeferredControl.v
+81 −29 src/test/vsrc/vcs/top.v
+9 −2 vcs.mk
+1 −1 verilator.mk
9 changes: 5 additions & 4 deletions src/test/scala/TopMain.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,9 @@ object TopMain extends App {
require(target != "")
target.substring(info.length()+1)
}
val board = parseArgs("BOARD", args)
val core = parseArgs("CORE", args)
val newArgs = DifftestModule.parseArgs(args)
val board = parseArgs("BOARD", newArgs)
val core = parseArgs("CORE", newArgs)

val s = (board match {
case "sim" => Nil
Expand All @@ -71,10 +72,10 @@ object TopMain extends App {
else {
ChiselGeneratorAnnotation(() => new Top)
}
var exe_args = args.filter{
var exe_args = newArgs.filter{
value => value.forall(char => char!='=')
}
(new ChiselStage).execute(args, Seq(generator)
(new ChiselStage).execute(newArgs, Seq(generator)
:+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
:+ FirtoolOption("--disable-annotation-unknown")
)
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