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What happened when three different ends, and why. #503
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See #486
Please list full messages for us to help you.
Simply as it says, the assertion fails. |
Here is the tail of a log:
I guess there is a mismatch of Thank you sir. |
Please list the full message here. Otherwise, we are unable to help. |
1.2 We set But we use DiffTest to execute it, the instruction in pc=0x800000010 is not changed, and we got abort latter. |
Please note the "In the last commit group" field in log files. Based on A, mentioned above, I test B, C & D. B: Do something before
B-1: |
C: load imm:
If we don't set
We set
|
I am not sure whether the bugs are in XiangShan or NEMU, or the DiffTest. Because I got the 1.2 ABORT first, and I checked it got those results. |
For us as the cosim framework developers, we are responsible for ensuring DiffTest reports the correct error information to the user. We will not respond to any bugs you encountered on any designs, because that is out of the scope of this repo. Thus, if you are facing DiffTest errors on XiangShan with some error messages, please raise an issue in the XiangShan repo. If you are facing a case where difftest aborts but no error information is shown, please list the full message here, so that we can help see what happens. |
Thanks for your reply. |
Please also redirect stderr to file and provide us with full messages. |
Run |
In your log file: Though this log seems different from the last zip file you provided, I believe DiffTest shows the correct error information for this case. |
Thanks. |
Related component: cosim with a REF
Describe the question
I built the env by xs-env and run emu to test xiangshan, the ref model is NEMU. Recently, I encountered 3 different ends I have never met.
When instr trace & ref regs are printed:
1.1 "Core 0 dump: critical_error raise" printed.
What happened to here? Why this happened?
1.2 "Core 0: [31mABORT at pc = "
Usually, when "Core 0: [31mABORT at pc = " printed, it will print "xxx different at pc =", but this time, it did not print it.
This is abnormal, isn't it?
“Assertion failed at /home/xs-env/XiangShan/build/rtl/DCache.sv:1430. The simulation stopped. There might be some assertion failed.”:
What happened and why? Is there a bug triggered it?
What you expect us (DiffTest developers) to do for you
I need someone can help me to figure out those questions.
Thanks a lot.
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