Move FMC/SFP interfaces to separate package to pass HDL tests

PandABlocks · May 22, 2024 · 040f823 · 040f823
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commit 040f823
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Showing 18 changed files with 127 additions and 99 deletions.
diff --git a/common/hdl/defines/interface_types.vhd b/common/hdl/defines/interface_types.vhd
@@ -0,0 +1,110 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package interface_types is
+
+    -- FMC Block Record declarations
+
+    type FMC_interface is
+      record
+        FMC_PRSNT       : std_logic;
+        FMC_LA_P        : std_logic_vector(33 downto 0);
+        FMC_LA_N        : std_logic_vector(33 downto 0);
+        FMC_CLK0_M2C_P  : std_logic;
+        FMC_CLK0_M2C_N  : std_logic;
+        FMC_CLK1_M2C_P  : std_logic;
+        FMC_CLK1_M2C_N  : std_logic;
+      end record FMC_interface;
+
+    view FMC_Module of FMC_interface is
+        FMC_PRSNT       : in;
+        FMC_LA_P        : inout;
+        FMC_LA_N        : inout;
+        FMC_CLK0_M2C_P  : inout;
+        FMC_CLK0_M2C_N  : inout;
+        FMC_CLK1_M2C_P  : in;
+        FMC_CLK1_M2C_N  : in;
+    end view FMC_Module;
+
+    constant FMC_init : FMC_interface;
+
+    type FMC_array is array (natural range <>) of FMC_interface;
+
+    type FMC_ARR_REC is record
+        FMC_ARR : FMC_array;
+    end record FMC_ARR_REC;
+
+    view FMC_MOD_ARR of FMC_ARR_REC is
+        FMC_ARR: view (FMC_Module);
+    end view;
+
+    -- SFP Block Record declarations
+
+    type MGT_interface is
+      record
+        SFP_LOS     : std_logic;
+        GTREFCLK    : std_logic;
+        RXN_IN      : std_logic;
+        RXP_IN      : std_logic;
+        TXN_OUT     : std_logic;
+        TXP_OUT     : std_logic;
+        MGT_REC_CLK : std_logic;
+        LINK_UP     : std_logic;
+        TS_SEC      : std_logic_vector(31 downto 0);
+        TS_TICKS    : std_logic_vector(31 downto 0);
+        MAC_ADDR    : std_logic_vector(47 downto 0);
+        MAC_ADDR_WS : std_logic;
+      end record MGT_interface;
+
+    view MGT_Module of MGT_interface is
+        SFP_LOS     : in;
+        GTREFCLK    : in;
+        RXN_IN      : in;
+        RXP_IN      : in;
+        TXN_OUT     : out;
+        TXP_OUT     : out;
+        MGT_REC_CLK : out;
+        LINK_UP     : out;
+        TS_SEC      : out;
+        TS_TICKS    : out;
+        MAC_ADDR    : in;
+        MAC_ADDR_WS : in;
+    end view MGT_Module;
+
+    constant MGT_init : MGT_interface;
+
+    type MGT_array is array (natural range <>) of MGT_interface;
+
+    type MGT_ARR_REC is record
+        MGT_ARR : MGT_array;
+    end record MGT_ARR_REC;
+
+    view MGT_MOD_ARR of MGT_ARR_REC is
+        MGT_ARR: view (MGT_Module);
+    end view;
+end;
+
+package body interface_types is
+
+    constant FMC_init : FMC_interface := (  FMC_PRSNT => '0',
+                                            FMC_LA_P => (others => 'Z'),
+                                            FMC_LA_N => (others => 'Z'),
+                                            FMC_CLK0_M2C_P => 'Z',
+                                            FMC_CLK0_M2C_N => 'Z',
+                                            FMC_CLK1_M2C_P => '0',
+                                            FMC_CLK1_M2C_N => '0');
+
+    constant MGT_init : MGT_interface := (  SFP_LOS => '0',
+                                            GTREFCLK => '0',
+                                            RXN_IN => '0',
+                                            RXP_IN => '0',
+                                            TXN_OUT => 'Z',
+                                            TXP_OUT => 'Z',
+                                            MGT_REC_CLK => '0',
+                                            LINK_UP => '0',
+                                            TS_SEC => (others => '0'),
+                                            TS_TICKS => (others => '0'),
+                                            MAC_ADDR => (others => '0'),
+                                            MAC_ADDR_WS => '0');
+
+end;
diff --git a/common/hdl/defines/top_defines.vhd b/common/hdl/defines/top_defines.vhd
@@ -62,103 +62,6 @@ end record;
 --
 -- TYPEs :
 --
-
--- FMC Block Record declarations
-
-type FMC_interface is
-  record
-    FMC_PRSNT       : std_logic;
-    FMC_LA_P        : std_logic_vector(33 downto 0);
-    FMC_LA_N        : std_logic_vector(33 downto 0);
-    FMC_CLK0_M2C_P  : std_logic;
-    FMC_CLK0_M2C_N  : std_logic;
-    FMC_CLK1_M2C_P  : std_logic;
-    FMC_CLK1_M2C_N  : std_logic;
-  end record FMC_interface;
-
-view FMC_Module of FMC_interface is
-    FMC_PRSNT       : in;
-    FMC_LA_P        : inout;
-    FMC_LA_N        : inout;
-    FMC_CLK0_M2C_P  : inout;
-    FMC_CLK0_M2C_N  : inout;
-    FMC_CLK1_M2C_P  : in;
-    FMC_CLK1_M2C_N  : in;
-end view FMC_Module;
-
-constant FMC_init : FMC_interface := (  FMC_PRSNT => '0',
-                                        FMC_LA_P => (others => 'Z'),
-                                        FMC_LA_N => (others => 'Z'),
-                                        FMC_CLK0_M2C_P => 'Z',
-                                        FMC_CLK0_M2C_N => 'Z',
-                                        FMC_CLK1_M2C_P => '0',
-                                        FMC_CLK1_M2C_N => '0');
-
-type FMC_array is array (natural range <>) of FMC_interface;
-
-type FMC_ARR_REC is record
-    FMC_ARR : FMC_array;
-end record FMC_ARR_REC;
-
-view FMC_MOD_ARR of FMC_ARR_REC is
-    FMC_ARR: view (FMC_Module);
-end view;
-
--- SFP Block Record declarations
-
-type MGT_interface is
-  record
-    SFP_LOS     : std_logic;
-    GTREFCLK    : std_logic;
-    RXN_IN      : std_logic;
-    RXP_IN      : std_logic;
-    TXN_OUT     : std_logic;
-    TXP_OUT     : std_logic;
-    MGT_REC_CLK : std_logic;
-    LINK_UP     : std_logic;
-    TS_SEC      : std_logic_vector(31 downto 0);
-    TS_TICKS    : std_logic_vector(31 downto 0);
-    MAC_ADDR    : std_logic_vector(47 downto 0);
-    MAC_ADDR_WS : std_logic;
-  end record MGT_interface;
-
-view MGT_Module of MGT_interface is
-    SFP_LOS     : in;
-    GTREFCLK    : in;
-    RXN_IN      : in;
-    RXP_IN      : in;
-    TXN_OUT     : out;
-    TXP_OUT     : out;
-    MGT_REC_CLK : out;
-    LINK_UP     : out;
-    TS_SEC      : out;
-    TS_TICKS    : out;
-    MAC_ADDR    : in;
-    MAC_ADDR_WS : in;
-end view MGT_Module;
-
-constant MGT_init : MGT_interface := (  SFP_LOS => '0',
-                                        GTREFCLK => '0',
-                                        RXN_IN => '0',
-                                        RXP_IN => '0',
-                                        TXN_OUT => 'Z',
-                                        TXP_OUT => 'Z',
-                                        MGT_REC_CLK => '0',
-                                        LINK_UP => '0',
-                                        TS_SEC => (others => '0'),
-                                        TS_TICKS => (others => '0'),
-                                        MAC_ADDR => (others => '0'),
-                                        MAC_ADDR_WS => '0');
-
-type MGT_array is array (natural range <>) of MGT_interface;
-
-type MGT_ARR_REC is record
-    MGT_ARR : MGT_array;
-end record MGT_ARR_REC;
-
-view MGT_MOD_ARR of MGT_ARR_REC is
-    MGT_ARR: view (MGT_Module);
-end view;
 
 type seq_t is
 record

diff --git a/common/templates/soft_blocks.vhd.jinja2 b/common/templates/soft_blocks.vhd.jinja2
@@ -7,6 +7,7 @@ use ieee.std_logic_1164.all;
 
 use work.addr_defines.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity soft_blocks is
 port (

diff --git a/modules/fmc_24vio/hdl/fmc_24vio_wrapper.vhd b/modules/fmc_24vio/hdl/fmc_24vio_wrapper.vhd
@@ -21,6 +21,7 @@ use unisim.vcomponents.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity fmc_24vio_wrapper is
 port (

diff --git a/modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd b/modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd
@@ -20,6 +20,7 @@ use unisim.vcomponents.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity fmc_acq427_wrapper is
 port (

diff --git a/modules/fmc_acq430/hdl/fmc_acq430_wrapper.vhd b/modules/fmc_acq430/hdl/fmc_acq430_wrapper.vhd
@@ -20,6 +20,7 @@ use unisim.vcomponents.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity fmc_acq430_wrapper is
 port (

diff --git a/modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd b/modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd
@@ -25,6 +25,7 @@ use unisim.vcomponents.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity fmc_loopback_wrapper is
 port (

diff --git a/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd b/modules/fmc_x4sfp/hdl/fmc_x4sfp_wrapper.vhd
@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
 
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity us_system_top is
 port (

diff --git a/modules/sfp_eventr/hdl/sfp_dls_eventr_wrapper.vhd b/modules/sfp_eventr/hdl/sfp_dls_eventr_wrapper.vhd
@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 library unisim;
 use unisim.vcomponents.all;

diff --git a/modules/sfp_loopback/hdl/sfp_loopback_wrapper.vhd b/modules/sfp_loopback/hdl/sfp_loopback_wrapper.vhd
@@ -5,6 +5,7 @@ use ieee.numeric_std.all;
 library work;
 use work.support.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity sfp_loopback_wrapper is
 port (

diff --git a/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd b/modules/sfp_panda_sync/hdl/sfp_panda_sync_wrapper.vhd
@@ -4,6 +4,7 @@ use ieee.std_logic_1164.all;
 
 library work;
 use work.top_defines.all;
+use work.interface_types.all;
 
 library unisim;
 use unisim.vcomponents.all;

diff --git a/modules/sfp_udpontrig/hdl/sfp_udpontrig_wrapper.vhd b/modules/sfp_udpontrig/hdl/sfp_udpontrig_wrapper.vhd
@@ -23,6 +23,7 @@ library IEEE;
 library work;
   use work.support.all;
   use work.top_defines.all;
+  use work.interface_types.all;
 
 library UNISIM;
 use UNISIM.vcomponents.all;  -- needed for OBUF instance

diff --git a/targets/PandABox/hdl/PandABox_top.vhd b/targets/PandABox/hdl/PandABox_top.vhd
@@ -18,6 +18,7 @@ use unisim.vcomponents.all;
 
 use work.addr_defines.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity PandABox_top is
 generic (

diff --git a/targets/ZedBoard/hdl/ZedBoard_top.vhd b/targets/ZedBoard/hdl/ZedBoard_top.vhd
@@ -18,6 +18,7 @@ use unisim.vcomponents.all;
 
 use work.addr_defines.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity ZedBoard_top is
 generic (

diff --git a/targets/xu5_st1/hdl/xu5_st1_top.vhd b/targets/xu5_st1/hdl/xu5_st1_top.vhd
@@ -18,6 +18,7 @@ use unisim.vcomponents.all;
 
 use work.addr_defines.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity xu5_st1_top is
 generic (

diff --git a/tests/hdl/regression_tests.tcl b/tests/hdl/regression_tests.tcl
@@ -56,6 +56,8 @@ add_files -norecurse \
     $TOP_DIR/common/hdl/defines \
     $APP_BUILD_DIR/autogen/hdl/top_defines_gen.vhd
 
+set_property FILE_TYPE "VHDL 2008" [get_files $TOP_DIR/common/hdl/defines/top_defines.vhd]
+
 # Loop through all the tests
 foreach test [array names tests] {
 

diff --git a/tests/hdl/single_test.tcl b/tests/hdl/single_test.tcl
@@ -35,8 +35,7 @@ add_files -norecurse \
     $TOP_DIR/common/hdl/defines \
     $APP_BUILD_DIR/autogen/hdl/top_defines_gen.vhd
 
-
-
+set_property FILE_TYPE "VHDL 2008" [get_files $TOP_DIR/common/hdl/defines/top_defines.vhd]
 
 puts  "###############################################################################################";
 puts  "                                           $test"                                               ;

diff --git a/tests/python/test_data/app-expected/hdl/soft_blocks.vhd b/tests/python/test_data/app-expected/hdl/soft_blocks.vhd
@@ -7,6 +7,7 @@ use ieee.std_logic_1164.all;
 
 use work.addr_defines.all;
 use work.top_defines.all;
+use work.interface_types.all;
 
 entity soft_blocks is
 port (