fixed stray TAB characters

PandABlocks · Feb 11, 2021 · 3954286 · 3954286
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commit 3954286
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Showing 18 changed files with 80 additions and 80 deletions.
diff --git a/common/hdl/shifter_in.vhd b/common/hdl/shifter_in.vhd
@@ -66,12 +66,12 @@ begin
                 smpl_hold <= (others => '0');
             -- Shift data when enabled.
             elsif (enable_i = '1') then
-				if (clock_i = '1') then
-					if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
-						smpl_hold <= smpl_hold(DW-2 downto 0) & data_i;
-					else
-						smpl_hold <= smpl_hold(DW-2 downto 0) & (data_i xor smpl_hold(0));
-					end if;
+                if (clock_i = '1') then
+                    if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
+                        smpl_hold <= smpl_hold(DW-2 downto 0) & data_i;
+                    else
+                        smpl_hold <= smpl_hold(DW-2 downto 0) & (data_i xor smpl_hold(0));
+                    end if;
                 end if;
             end if;
         end if;

diff --git a/common/templates/block_wrapper.vhd.jinja2 b/common/templates/block_wrapper.vhd.jinja2
@@ -109,7 +109,7 @@ begin
     {% elif field in filter_fields("pos_mux") %}
             {{ pad(field.name+"_from_bus") }} => {{ field.name }}(I),
     {% else %}
-		{% for register in field.numbered_registers() %}
+        {% for register in field.numbered_registers() %}
             {{ pad(register.name) }} => {{ register.name }}(I),
             {% if "read" not in field.type %}
             {{ pad(register.name + "_wstb") }} => {{ register.name }}_wstb(I),
@@ -133,11 +133,11 @@ begin
         {{ entity }} : entity work.{{ entity }}
         port map (
 {% for field in fields %}
-	{% if field in filter_fields("bit_mux") %}
+    {% if field in filter_fields("bit_mux") %}
             {{ pad(field.name +"_i") }} => {{ field.name }}(I)(0),
-	{% elif field in filter_fields("pos_mux") %}
+    {% elif field in filter_fields("pos_mux") %}
             {{ pad(field.name +"_i") }} => {{ field.name }}(I),
-	{% elif field in filter_fields(".*_out") %}
+    {% elif field in filter_fields(".*_out") %}
             {{ pad(field.name + "_o") }} => {{ field.name }}_o(I),
     {% else %}
         {% for register in field.numbered_registers() %}

diff --git a/common/templates/hdl_timing.v.jinja2 b/common/templates/hdl_timing.v.jinja2
@@ -15,10 +15,10 @@ always #4 clk_i = ~clk_i;
     {% if field.type == "bit_mux" %}
 reg         {{ field.name }};
     {% else %}
-	    {% for register in field.numbered_registers() %}
+        {% for register in field.numbered_registers() %}
 reg  [31:0] {{ register.name }};
-	    {% endfor %}
-	{% endif %}
+        {% endfor %}
+    {% endif %}
 {% endfor %}
 
 // Outputs

diff --git a/common/templates/pcap_hdl_timing.v.jinja2 b/common/templates/pcap_hdl_timing.v.jinja2
@@ -37,15 +37,15 @@ reg              reset = 1;
     {% if field.type == "bit_mux" %}
 reg         {{ field.name }};
     {% else %}
-	    {% for register in field.registers %}
-	        {% if register.number >= 0 %}
+        {% for register in field.registers %}
+            {% if register.number >= 0 %}
 reg  [31:0] {{ register.name }};
-			{% endif %}
-	    {% endfor %}
-	    {% if field.type == "time" %}
+            {% endif %}
+        {% endfor %}
+        {% if field.type == "time" %}
 wire [47:0] {{ field.name }};
-	    {% endif %}
-	{% endif %}
+        {% endif %}
+    {% endif %}
 {% endfor %}
 
 // Outputs
@@ -73,7 +73,7 @@ reg         {{ field.name }}_err;   //Error signal
         {% for register in field.registers %}
             {% if register.number >= 0 %}
 reg         {{ register.name }}_wstb;
-			{% endif %}
+            {% endif %}
         {% endfor %}
         {% if field.type == "time" %}
 wire        {{ field.name }}_wstb;

diff --git a/common/templates/top_defines.vhd.jinja2 b/common/templates/top_defines.vhd.jinja2
@@ -115,7 +115,7 @@ type SFP_output_interface is
   record
     TXN_OUT     : std_logic;
     TXP_OUT     : std_logic;
-	EVR_REC_CLK : std_logic;
+    EVR_REC_CLK : std_logic;
     LINK_UP     : std_logic;
   end record SFP_output_interface;
 

diff --git a/modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd b/modules/fmc_acq427/hdl/fmc_acq427_wrapper.vhd
@@ -30,14 +30,14 @@ port (
     bit_bus_i           : in  bit_bus_t;
     pos_bus_i           : in  pos_bus_t;
     -- Outputs to PosBus from FMC
-	in_val1_o				: out std32_array(0 downto 0);
-	in_val2_o				: out std32_array(0 downto 0);
-	in_val3_o				: out std32_array(0 downto 0);
-	in_val4_o				: out std32_array(0 downto 0);
-	in_val5_o				: out std32_array(0 downto 0);
-	in_val6_o				: out std32_array(0 downto 0);
-	in_val7_o				: out std32_array(0 downto 0);
-	in_val8_o				: out std32_array(0 downto 0);
+    in_val1_o               : out std32_array(0 downto 0);
+    in_val2_o               : out std32_array(0 downto 0);
+    in_val3_o               : out std32_array(0 downto 0);
+    in_val4_o               : out std32_array(0 downto 0);
+    in_val5_o               : out std32_array(0 downto 0);
+    in_val6_o               : out std32_array(0 downto 0);
+    in_val7_o               : out std32_array(0 downto 0);
+    in_val8_o               : out std32_array(0 downto 0);
     -- Outputs to BitBus from FMC
     in_ttl_o               : out std_logic_vector(0 downto 0);
     -- Memory Bus Interface

diff --git a/modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd b/modules/fmc_loopback/hdl/fmc_loopback_wrapper.vhd
@@ -236,7 +236,7 @@ port map (
     FMC_CLK0            => FREQ_VAL(1),
     FMC_CLK1            => FREQ_VAL(2),
     EXT_CLK             => FREQ_VAL(3),
-	FMC_MAC_LO          => MAC_LO,
+    FMC_MAC_LO          => MAC_LO,
     FMC_MAC_HI          => MAC_HI,
     SOFT_RESET          => open,
     SOFT_RESET_WSTB     => SOFT_RESET,

diff --git a/modules/sfp_dls_eventr/hdl/sfp_dls_eventr_wrapper.vhd b/modules/sfp_dls_eventr/hdl/sfp_dls_eventr_wrapper.vhd
@@ -17,7 +17,7 @@ port (
     -- System Bus
     bit_bus_i           : in  bit_bus_t;
     pos_bus_i           : in  pos_bus_t;
-	-- Outputs to BitBus from FMC
+    -- Outputs to BitBus from FMC
     bit1_o              : out std_logic_vector(0 downto 0);
     bit2_o              : out std_logic_vector(0 downto 0);
     bit3_o              : out std_logic_vector(0 downto 0);

diff --git a/old/tests/sim/panda_biss/bench/glbl.v b/old/tests/sim/panda_biss/bench/glbl.v
@@ -50,17 +50,17 @@ module glbl ();
     assign (weak1, weak0) PRLD = PRLD_int;
 
     initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
+    GSR_int = 1'b1;
+    PRLD_int = 1'b1;
+    #(ROC_WIDTH)
+    GSR_int = 1'b0;
+    PRLD_int = 1'b0;
     end
 
     initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
+    GTS_int = 1'b1;
+    #(TOC_WIDTH)
+    GTS_int = 1'b0;
     end
 
 endmodule
diff --git a/old/tests/sim/panda_slowctrl/bench/glbl.v b/old/tests/sim/panda_slowctrl/bench/glbl.v
@@ -50,17 +50,17 @@ module glbl ();
     assign (weak1, weak0) PRLD = PRLD_int;
 
     initial begin
-	GSR_int = 1'b1;
-	PRLD_int = 1'b1;
-	#(ROC_WIDTH)
-	GSR_int = 1'b0;
-	PRLD_int = 1'b0;
+    GSR_int = 1'b1;
+    PRLD_int = 1'b1;
+    #(ROC_WIDTH)
+    GSR_int = 1'b0;
+    PRLD_int = 1'b0;
     end
 
     initial begin
-	GTS_int = 1'b1;
-	#(TOC_WIDTH)
-	GTS_int = 1'b0;
+    GTS_int = 1'b1;
+    #(TOC_WIDTH)
+    GTS_int = 1'b0;
     end
 
 endmodule
diff --git a/targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd b/targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd
@@ -70,8 +70,8 @@ begin
             return X"10";
         when "100"  => -- Pass
             return X"07";
-		when "101" => -- Data passthrough (same as SSI)
-			return X"28";
+        when "101" => -- Data passthrough (same as SSI)
+            return X"28";
         when others =>
             return X"00";
     end case;

diff --git a/targets/PandABox/hdl/biss_slave.vhd b/targets/PandABox/hdl/biss_slave.vhd
@@ -116,7 +116,7 @@ begin
             health_biss_slave<=TO_SVECTOR(1,32);--default error 
         else
            case SM_DATA is
-		   
+           
                -- SYNCH STATE
                when STATE_SYNCH =>
                    if (enable_i = '1') then
@@ -153,7 +153,7 @@ begin
                       SM_DATA <= STATE_SYNCH;
                       sck_timeout_cnt<=c_MAX_TIMEOUT;
                    end if;
-		   
+           
                -- ACK STATE
                when STATE_ACK =>
                    -- ACK = 0
@@ -195,7 +195,7 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- ZERO STATE
                when STATE_ZERO =>
                    -- ZERO = 0
@@ -218,22 +218,22 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- DATA STATE
                when STATE_DATA =>
                    -- Transmit data
                    if (biss_sck_rising_edge = '1') then
                        data_cnt <= data_cnt -1;
-					   if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
-					       biss_dat <= posn_latched(to_integer(data_cnt-9));
-					   else
-					       -- gray encoding
-					       if(data_cnt = (unsigned(BITS) + c_nEnW_size + c_CRC_size)) then
-					           biss_dat <= posn_latched(to_integer(data_cnt-9));
-					       else
-					           biss_dat <= posn_latched(to_integer(data_cnt-9)) xor posn_latched(to_integer(data_cnt-8));
-					       end if;
-					   end if;
+                       if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
+                           biss_dat <= posn_latched(to_integer(data_cnt-9));
+                       else
+                           -- gray encoding
+                           if(data_cnt = (unsigned(BITS) + c_nEnW_size + c_CRC_size)) then
+                               biss_dat <= posn_latched(to_integer(data_cnt-9));
+                           else
+                               biss_dat <= posn_latched(to_integer(data_cnt-9)) xor posn_latched(to_integer(data_cnt-8));
+                           end if;
+                       end if;
                        if (data_cnt = 9) then
                            data_enable <= '0';
                            nEnW_enable <= '1';
@@ -253,7 +253,7 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- nE(error flag) nW(warning flag) STATE
                when STATE_nEnW =>
                    -- Transmit the error and warning bits
@@ -278,7 +278,7 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- CRC STATE
                when STATE_CRC =>
                    -- Transmit the calculated CRC value
@@ -302,7 +302,7 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- STOP STATE
                when STATE_STOP =>
                    -- STOP = 0 during timeout
@@ -323,7 +323,7 @@ begin
                    else
                        sck_timeout_cnt<=sck_timeout_cnt-1;
                    end if;
-		   
+           
                -- TIMEOUT STATE
                when STATE_TIMEOUT =>
                    -- STOP = 0 during timeout

diff --git a/targets/PandABox/hdl/dcard_interface.vhd b/targets/PandABox/hdl/dcard_interface.vhd
@@ -185,7 +185,7 @@ begin
                     outenc_ctrl(I) <= outenc_dir(I) & "10";
 --                when "100"  =>                        -- Pass-Through
 --                    outenc_ctrl(I) <= "000";
-				when "101" =>
+                when "101" =>
                     outenc_ctrl(I) <= "011";          -- DATA PassThrough
                 when others =>
                     outenc_ctrl(I) <= "000";

diff --git a/targets/PandABox/hdl/encoders_block.vhd b/targets/PandABox/hdl/encoders_block.vhd
@@ -116,7 +116,7 @@ INENC_CONN_OUT_o <= STATUS(0);
 
 -- Certain parameter changes must initiate a block reset.
 reset <= reset_i or OUTENC_PROTOCOL_WSTB or OUTENC_BITS_WSTB or INENC_PROTOCOL_WSTB
-		 or OUTENC_ENCODING_WSTB or INENC_ENCODING_WSTB
+         or OUTENC_ENCODING_WSTB or INENC_ENCODING_WSTB
          or CLK_PERIOD_WSTB or FRAME_PERIOD_WSTB or INENC_BITS_WSTB;
 
 DCARD_TYPE <= x"0000000" & '0' & DCARD_MODE_i(3 downto 1);

diff --git a/targets/PandABox/hdl/ssi_slave.vhd b/targets/PandABox/hdl/ssi_slave.vhd
@@ -110,11 +110,11 @@ begin
                     if (shift_clock = '1') then
                         shift_reg <= shift_reg(30 downto 0) & shift_reg(31);
                         shift_counter <= shift_counter + 1;
-						if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
-							ssi_dat_o <= shift_reg(to_integer(unsigned(BITS))-1);
-						else
-							ssi_dat_o <= data_prev xor shift_reg(to_integer(unsigned(BITS))-1);
-						end if;
+                        if ((ENCODING=c_UNSIGNED_BINARY_ENCODING) or (ENCODING=c_SIGNED_BINARY_ENCODING)) then
+                            ssi_dat_o <= shift_reg(to_integer(unsigned(BITS))-1);
+                        else
+                            ssi_dat_o <= data_prev xor shift_reg(to_integer(unsigned(BITS))-1);
+                        end if;
 
                         data_prev <= shift_reg(to_integer(unsigned(BITS))-1);
                     end if;

diff --git a/targets/PandABox/hdl/ssi_sniffer.vhd b/targets/PandABox/hdl/ssi_sniffer.vhd
@@ -171,7 +171,7 @@ begin
                 if (I < intBITS) then
                     posn_o(I) <= data(I);
                 else
-					posn_o(I) <= data(intBITS-1);
+                    posn_o(I) <= data(intBITS-1);
                 end if;
             END LOOP;
         end if;

diff --git a/targets/PandABox/hdl/ttlin_top.vhd b/targets/PandABox/hdl/ttlin_top.vhd
@@ -28,9 +28,9 @@ port (
     --Memory Bus Interface
     write_strobe_i      : in  std_logic;
     write_address_i     : in  std_logic_vector(PAGE_AW-1 downto 0);
-	write_data_i        : in  std_logic_vector(31 downto 0);
-	--Memory interface
-	slow_tlp_o          : out slow_packet;
+    write_data_i        : in  std_logic_vector(31 downto 0);
+    --Memory interface
+    slow_tlp_o          : out slow_packet;
     -- TTL I/O
     pad_i               : in  std_logic_vector(TTLIN_NUM-1 downto 0);
     val_o               : out std_logic_vector(TTLIN_NUM-1 downto 0)

diff --git a/tests/hdl/top_defines.vhd b/tests/hdl/top_defines.vhd
@@ -114,7 +114,7 @@ type SFP_output_interface is
   record
     TXN_OUT     : std_logic;
     TXP_OUT     : std_logic;
-	EVR_REC_CLK : std_logic;
+    EVR_REC_CLK : std_logic;
     LINK_UP     : std_logic;
   end record SFP_output_interface;