The DisplayPort IP-core is a resource optimized DisplayPort solution for FPGA devices.
The DP IP-core will autonome handle the link training and bring up of the video stream.
The thin host driver has a simple API, which is used by the application to interact with the DP IP-core.
- DisplayPort 1.4
- Source (DPTX) and Sink (DPRX)
- RBR, HBR, HBR2 and HBR3 linerates
- Support for 1, 2 and 4 DP lanes
- Native video and AXI stream video interfaces
- Single Stream transport mode (SST)
- Dual and quad pixels per clock
- Video toolbox (VTB)
- Timing generator
- Test pattern generator
- Clock recovery
- Supported devices
- AMD UltraScale+
- AMD Artix-7
- Lattice CertusPro-NX
- Intel Cyclone 10 GX
- Intel Arria 10 GX
The documentation is available online at www.parretto.com/dp
This License will apply to the use of the IP-core (as defined in the License).
Please read the License carefully so that you know what your rights and obligations are when using the IP-core.
The acceptance of this License constitutes a valid and binding agreement between Parretto and you for the use of the IP-core.
If you download and/or make any use of the IP-core you agree to be bound by this License.
The License is available for download at www.parretto.com/license
Parretto grants you, as the Licensee, a free, non-exclusive, non-transferable, limited right to use the IP-core
solely for internal business purposes for the term and conditions of the License.
You are also allowed to create Modifications for internal business purposes, but explicitly only under the conditions of art. 3.2.
You are, however, obliged to pay the License Fees to Parretto for the use of the IP-core, or any Modification, in, or embodied in,
a physical or non-tangible product or service that has substantial commercial, industrial or non-consumer uses.
Send an email to [email protected]
(c) 2021 - 2024 by Parretto B.V.