This project is an implementation of a Single Cycle CPU utilizing the RISC-V ISA. The design is based off of the RV32I implementation as outlined in the RISC-V Instruction Set Manual. Therefor making this a 32-bit cpu, written all in Verilog. This project was mostly made as a hobby and educational purposes, and I talk more about that and the design process here on my website.
This CPU is based off a Harvard architecture opting for separate instruction and data memory. For simplicity the image below just outlines the Datapath with no control logic.
- A general understanding of the RV32I implementation as referenced in the RISC-V Instruction Set Manual may help with understanding of this project.
- A Verilog synthesis tool is needed for this project i used Icarus Verilog.
- GTKWave or a waveform viewer of your choice (All my scripts are set up with GTKWave).
- 32 bit RISC-V Toolchain (guide to build the toolchain) for more details on how to compile assembly or C refer to programs folder.
Note: This project is currently under active development and I'm not perfect ;)