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This patch adds support for the Zihintpause extension to the riscv64 architecture. This extension is a mandatory instruction set extension in the RVA23 architecture profile (RVA23 profile), and its PAUSE instruction can reduce energy consumption while executing spin-wait code sequences.


🔄 This is a mirror of upstream PR golang#75616

This patch adds support for the Zihintpause extension to the riscv64 architecture. This extension is a mandatory instruction set extension in the RVA23 architecture profile (RVA23 profile), and its  PAUSE instruction can reduce energy consumption while executing spin-wait code sequences.
@austinderek austinderek force-pushed the master branch 27 times, most recently from 3e4540b to 37c78b5 Compare September 26, 2025 20:03
@austinderek austinderek force-pushed the master branch 27 times, most recently from b497a29 to 5bf50a0 Compare October 11, 2025 09:02
@austinderek austinderek deleted the Zihintpause_asm branch October 11, 2025 09:03
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staging bot commented Oct 11, 2025

HackerOne Code Security Review

🟢 Scan Complete: 1 Issue(s)
🟠 Validation Complete: One or more Issues looked potentially actionable, so this was escalated to our network of engineers for manual review. Once this is complete you'll see an update posted.

Here's how the code changes were interpreted and info about the tools used for scanning.

📖 Summary of Changes The changes involve adding PAUSE instruction support for RISC-V architecture. Specifically, a new PAUSE instruction was introduced in the assembly test data file, and corresponding instruction constants were added to the CPU-related Go file, including compressed floating-point load/store instructions and a pseudo-instruction for PAUSE.
File Summary
src/cmd/asm/internal/asm/testdata/riscv64.s The file now includes a new instruction, PAUSE, under the "10.1: Zihintpause Extension for Pause Hint" section, which was not present in the previous version.
src/cmd/internal/obj/riscv/cpu.go Added compressed floating-point load and store instructions (ACFLW, ACFLD, ACFSW, ACFSD) and a new pseudo-instruction APAUSE to the instruction set constants.
ℹ️ Issues Detected

NOTE: These may not require action!

Below are unvalidated results from the Analysis Tools that ran during the latest scan for transparency. We investigate each of these for accuracy and relevance before surfacing them as a potential problem.

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File & Line Issue
src/cmd/asm/internal/asm/testdata/riscv64.s Line 199 The added PAUSE instruction (lines 198-199) is a security-relevant addition as it implements the Zihintpause extension for RISC-V. The PAUSE hint is used to improve performance in spin-wait loops by reducing energy consumption and potentially improving performance of simultaneous multithreading. While this is not a direct security vulnerability, improper implementation of spin locks can lead to denial of service conditions or resource exhaustion. The PAUSE instruction helps mitigate these risks by making spin-wait loops more efficient.
🧰 Analysis tools

⏱️ Latest scan covered changes up to commit f504fdd (latest)

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