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@Purdue-SoCET

Purdue System on Chip Extension Technologies

A student team working on designing and testing an SoC at Purdue University

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  1. RISCVBusiness RISCVBusiness Public

    Forked from JakeStevens/RISCVBusiness

    SystemVerilog 8 3

  2. vortex vortex Public

    Forked from vortexgpgpu/vortex

    Verilog 4 1

  3. AFTx06_Caravel AFTx06_Caravel Public

    Verilog 3 2

  4. tensor-core tensor-core Public

    SystemVerilog 3

  5. AFTx05_Public AFTx05_Public Public

    Verilog 2 1

  6. SAFE SAFE Public

    Python 2 2

Repositories

Showing 10 of 52 repositories
  • AXI-UVM Public
    Purdue-SoCET/AXI-UVM’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Apr 9, 2025
  • tensor-core Public
    Purdue-SoCET/tensor-core’s past year of commit activity
    SystemVerilog 3 0 0 1 Updated Apr 9, 2025
  • RISCVBusiness Public Forked from JakeStevens/RISCVBusiness
    Purdue-SoCET/RISCVBusiness’s past year of commit activity
    SystemVerilog 8 8 1 (1 issue needs help) 6 Updated Apr 9, 2025
  • vortexS25 Public Forked from vortexgpgpu/vortex
    Purdue-SoCET/vortexS25’s past year of commit activity
    Verilog 0 Apache-2.0 308 0 0 Updated Apr 9, 2025
  • gpgpu-sim_distribution Public Forked from gpgpu-sim/gpgpu-sim_distribution

    GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

    Purdue-SoCET/gpgpu-sim_distribution’s past year of commit activity
    C++ 0 547 0 0 Updated Apr 9, 2025
  • intro-2-stopwatch Public
    Purdue-SoCET/intro-2-stopwatch’s past year of commit activity
    C++ 1 0 0 0 Updated Apr 9, 2025
  • GPU_Analysis Public
    Purdue-SoCET/GPU_Analysis’s past year of commit activity
    Python 0 0 0 0 Updated Apr 8, 2025
  • chiplet-components Public
    Purdue-SoCET/chiplet-components’s past year of commit activity
    SystemVerilog 1 0 0 0 Updated Apr 7, 2025
  • xv6-rv32 Public Forked from x653/xv6-rv32

    Port of MIT's xv6 OS to 32 bit RISC V

    Purdue-SoCET/xv6-rv32’s past year of commit activity
    C 0 17 0 0 Updated Apr 7, 2025
  • intro-socet Public
    Purdue-SoCET/intro-socet’s past year of commit activity
    SystemVerilog 0 1 0 0 Updated Apr 6, 2025
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