[PARTSELECT PLUS MINUS FIX] Fixed the MSB or LSB computation for the …

[loopyK1ng]

Fixed the MSB or LSB computation for the indexed vector partselect for Verilog. The second value is not a direct offset but the width of the selected part. So the value needs to be decreased by 1 before adding or subtracting it from the base.

Example Code:
module.v

module top
  (
   input wire clk, 
   input wire rstn,
   input wire [31:0] in,
   input wire [31:0] key_in,
   output reg [31:0] out
  );

  reg taint [31:0] key;

  assign key = key_in;

  always
  begin
    out[15-:16] = in[15-:16] & key[0+:16];
    out[31:16] = in[15:0] | key[15:0];
  end
endmodule

The first indices for OUT result in 15 (MSB) and -1 (LSB). Same for the first in. Additionally, 0+:16 results in 0 (LSB) and 16 (MSB).

Also contributed and a big thanks to:
@GorgeousWalrus

[shtaxxx]

I think inc_value should not be the first class object of Python.
In the following case, Minus object of Pyverilog is better.

         # original
         inc_value = p[5]
         inc_value.value = str(int(inc_value.value)-1)
         p[0] = Partselect(p[1], p[3], Plus(p[3], inc_value), lineno=p.lineno(1))
         # proposal
         inc_value = Minus(p[5], IntConst('1'))
         p[0] = Partselect(p[1], p[3], Plus(p[3], inc_value), lineno=p.lineno(1))

[loopyK1ng]

You are right. Included your suggestions.

[loopyK1ng]

Is there still something missing?